PA7536 Datasheet, PDF (1/10 Pages) Anachip Corp – PEEL Array-TM Programmable Electrically Erasable Logic Array

PA7536 PEEL Array™
Programmable Electrically Erasable Logic Array
Versatile Logic Array Architecture
- 12 I/Os, 14 inputs, 36 registers/latches
- Up to 36 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
Ideal for Combinatorial, Synchronous and
Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, multiplexers and
other wide-gate functions
High-Speed Commercial and Industrial Versions
- As fast as 9ns/15ns (tpdi/tpdx), 83.3MHz (f_MAX)
- Industrial grade available for 4.5 to 5.5V V_CC and
-40 to +85 °C temperatures
CMOS Electrically Erasable Technology
- Reprogrammable in 28-pin DIP, SOIC and PLCC
packages
Flexible Logic Cell
- Up to 3 output functions per logic cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
- Sum-of-products logic for output enables
Development and Programmer Support
- Anachip WinPLACE Development Software
- Fitters for ABEL and other software
- Programming support by popular third-party
programmers
General Description
The PA7536 is a member of the Programmable Electrically
Erasable Logic (PEEL™) Array family based on ICT’s
CMOS EEPROM technology. PEEL™ Arrays free
designers from the limitations of ordinary PLDs by
providing the architectural flexibility and speed needed for
today’s programmable logic designs. The PA7536 offers a
versatile logic array architecture with 12 I/O pins, 14 input
pins and 36 registers/latches (12 buried logic cells, 12
Input registers/latches and 12 buried registers/latches). Its
logic array implements 50 sum-of-products logic functions
that share 64 product terms. The PA7536’s logic and I/O
cells (LCCs, IOCs) are extremely flexible offering up to
three output functions per cell (a total of 36 for all 12 logic
cells). Cells are configurable as D, T, and JK registers with
independent or global clocks, resets, presets, clock
polarity, and other special features, making the PA7536
suitable for a variety of combinatorial, synchronous and
asynchronous logic applications. The PA7536 offers pin
compatibility and super-set functionality to popular 28-pin
PLDs, such as the 26V12. Thus, designs that exceed the
architectures of such devices can be expanded upon. The
PA7536 supports speeds as fast as 9ns/15ns (tpdi/tpdx)
and 83.3MHz (f_MAX) at moderate power consumption
105mA (75mA typical). Packaging includes 28-pin DIP,
SOIC, and PLCC (see Figure 1). Development and
programming support for the PA7536 is provided by
Anachip and popular third-party development tool
manufacturers.
Figure 1. Pin Configuration
I/C L K 1
I
I
I
I
I
VCC
I
I
I
I
I
I
I
1
28
I/CLK2 I/CLK1
1
28
I/C L K 2
2
27
I/O
I
2
27
I/O
3
26
I/O
I
3
I
4
26
I/O
25
I/O
4
25
I/O
I
5
24
I/O
5
24
I/O
I
6
23
I/O
6
23
I/O
VCC
7
I
8
22
I/O
21
GND
7
22
I/O
I
9
20
I/O
8
21
GND
I
10
19
I/O
9
20
I/O
I
11
I
12
18
I/O
17
I/O
10
19
I/O
I
13
16
I/O
11
18
I/O
I
14
15
I/O
12
17
I/O
13
16
I/O
S O IC
14
15
I/O
DIP
I
I
VCC
I
I
I
I
4 3 2 1 28 27 26
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
I/O
I/O
I/O
I/O
GND
I/O
I/O
PLCC
08 -16 -0 01A
Figure 2. Block Diagram
I/CLK1
I
I
I
I
I
VCC
I
I
I
I
I
I
I
2 Input/
Global Clock Pins
12 Input Pins
Input
Cells
(IN C )
G lobal Cells
Input Cells
I/O Cells
Logic Control Cells
PA7536
I/CLK2
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
G lo ba l
C e lls
76 (38X2)
Array Inputs
true and
2
com plem ent
I/O
12
12
C e lls
12 I/O Pins
(IOC)
L o g ic
Array
12
Buried
logic
A
B
Logic
Control
C
C e lls
12
D
(LCC)
Logic functions
to I/O cells
2 sum terms
3 product term s
for Global Cells
48 sum term s
(four per LCC)
12
12 Logic Control Cells
up to 3 output functions per cell
(36 total output functions possible)
08-16-002A
1
04-02-052A