AS5011 Datasheet, PDF (8/16 Pages) ams AG – Low Power Integrated Hall IC for Human Interface Applications

AS5011
Data Sheet
7 I²C interface
The AS5011 supports the 2-wire I²C protocol without “repeat start” as a slave device, the host CPU (master) has to
initiate the data transfers. The 7-bit device address of the AS5011 is ‘1000 000’.
The SDA signal is bidirectional and is used to read and write the serial data. The SCL signal is the clock generated
by the host CPU, to synchronize the SDA data in read and write mode. The maximum I²C clock frequency is 4MHz,
data are triggered on the rising edge of SCL.
7.1 Interface operation
For both read and write data transfers consist of three phases:
1. The master sends a START command by pulling down SDA while SCL remains high. Then the 7-bit device
address is sent followed by a read/write bit indicator. In READ mode (r/w = ‘1’), the slave has to send the
data from its selected register. In WRITE mode (r/w = ‘0’), the master writes the data in the selected
register. The slave has to acknowledge by sending ‘0’ after the r/w bit from the master.
2. The slave register is selected by the second data sent by the master. The address has an 8-bit format. The
slave has to acknowledge by sending ‘0’ after the bit R0.
3. The 8-bit data is transferred from/to the slave selected register, depending on the r/w bit. At the end of the
8-bit data transfer, the master (read mode) or the slave (write mode) acknowledges by sending ‘1’. The
transfer ends when the master sends a STOP command by sending a low to high transition while SCL
remains high.
The AS5011 does not send any acknowledge after the device address or register address (ACK remains High) in
the following cases:
- Wrong address
- Write access to a read-only register
Figure 10: I²C bus Read and Write operation
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