AS8506 Datasheet, PDF (79/89 Pages) ams AG – Battery Cell Monitor and Balancer IC

Application Information
Figure 102:
Application Schematic
VSUP2
VSUP2
40
39
38
37
36
35
34
33
32
31
VREF_H
7
TSECH2
1 TSECH
V5V
30
V5V_U
TSECL2
2 TSECL
6
3 VCELL7
4 VCELL6
AS8506
MLF 6x6
REF_T 29
TU1
TEMP_IN1
28
TU2
TEMP_IN2
27
100nF
NTC
2-5uF
VSUP1
NTC
5
5 VCELL5
6 VCELL4
CELL_THL
26
CELL_THU
25
TU1
TU2
7 VCELL3
GND
CS
24
1
8 VCELL2
(Exposed Pad)
SCLK 23
V5V_U
VSUP1
9 VCELL1
SDI 22
10 ^C-GND
SDO ₂₁
11
12
13
14
15
16
17
18
19
20
Note: If slave has to
drive FD pin then SDI
has to be connected
local ground
VSUP1
40
39
38
37
36
35
34
33
32
31
TSECH1
VREF_H
1 TSECH
V5V
V5V
30
7
TSECL1
2 TSECL
3 VCELL7
6
4 VCELL6
AS8506
MLF 6x6
REF_T 29
TEMP_IN1
TL1
28
TEMP_IN2
TL2
27
100nF
2-5uF
NTC
NTC
5 VCELL5
5
6 VCELL4
CELL_THL 26
CELL_THU
25
TL1
TL2
7 VCELL3
8 VCELL2
GND
(Exposed Pad)
CS
24
SCLK 23
CS
SCLK
9 VCELL1
1
10 ^C-GND
SDI 22
SDI
SDO ₂₁
SDO
11
12
13
14
15
16
17
Optional Factory Setting for Active Balancing
Supply from Stack
TSECH1
100 mA load
TSECL1
TSECH2
100 mA load
TSECL2
18
19
20
Note: Open drain on
WAKE_IN pin in the µC or
Transistor as shown
above.
CS
SCLK
SDI
SDO
WAKE
BD
CVT_NOK
CLK
TRIG
Micro
Controller
100 V device
Converter
for active
balancing
Caution: In the application it’s recommended to connect the AS8506 devices stacked first and connect the
battery stack from bottom to top in sequence to avoid any possible damage of the system. While removing
the battery pack its strictly recommended to remove the battery pack from the top. Removing the battery
pack from bottom will damage the system.
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 79