NSD-1202 Datasheet, PDF (7/13 Pages) ams AG – Dual Piezo Motor Driver IC for SQL Series

NSD-1202
Data Sheet - Detailed Description
7.3 Register Map
The table below shows the registers which can be addressed over the I²C interface.
Description
Period count A
Pulse count A (high byte)¹
Pulse count A (low byte)
Period count B
Pulse count B (high byte)¹
Pulse count B (low byte)
Output voltage
Duty cycle A
Duty cycle B
Reserved register
Data Byte
Address
MSB
LSB
00h
X
X
X
X
X
X
X
X
01h
h
d
X
X
X
02h
X
X
X
X
X
X
X
X
03h
X
X
X
X
X
X
X
X
04h
h
d
X
X
X
05h
X
X
X
X
X
X
X
X
06h
X
X
X
X
X
X
07h
X
X
X
X
X
X
X
X
08h
X
X
X
X
X
X
X
X
10h
X
X
X
X
X
X
X
X
1. The master clock doubling bit (‘h’) of both registers 01h and 04h must set in order for the doubling to take affect (even if only driving one
motor). Do not use clock doubling if the master clock has a frequency > 10 MHz.
7.4 Output Drivers
The output drivers operate rail to rail and are capable of driving a large capacitive load. In power-down mode the output drivers are pulled to
ground. The same applies when the motor is off.
Symbol
CLOAD
Parameter
Conditions
Min
Typ
Rise/fall time
CLOAD 600pF
25
100
Load capacitance
The load capacitance may be lower
than 500pF but the lower the value 500
600
the shorter the rise time.
Switching frequency
The accuracy of switching frequency 140
170
Switching frequency step
and phase shift will be defined
depending on master clock
0.98 1.45
Switching frequency duty cycle
frequency; the given values are for
20MHz master clock. Lower master
1
Duty cycle accuracy
clock frequencies give higher
-1
deviations. For Squiggle applications
Phase shift
20MHz clock is required, 10 MHz can
±90
Phase shift error
be used with the clock doubling
feature.
Clock doubling feature may be
Master clock frequency (CLK)
employed when using a 10MHz or
1
20
less master clock frequency
Max
Units
250
ns
700
pF
180
kHz
1.61
kHz
50
%
+1
%
deg
±3
deg
20
MHz
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