AS3709 Datasheet, PDF (60/74 Pages) ams AG – μPMIC with 5 DCDC and 2 LDOs

Register Description
Figure 80:
RegStatus Register (Address 73h)
Addr: 73h
Bit Bit Name
7:5
-
4
sd5_lv
3
sd4_lv
2
sd3_lv
1
sd2_lv
0
sd1_lv
RegStatus
Default Access Bit Description
‘b000
0
0
0
0
0
N/A
Do not use
RO
Bit is set when voltage of SD5 drops below low voltage
threshold (-5%) (1msec debounce time default)
RO
Bit is set when voltage of SD4 drops below low voltage
threshold (-5%) (1msec debounce time default)
RO
Bit is set when voltage of SD3 drops below low voltage
threshold (-5%) (1msec debounce time default)
RO
Bit is set when voltage of SD2 drops below low voltage
threshold (-5%) (1msec debounce time default)
RO
Bit is set when voltage of SD1 drops below low voltage
threshold (-5%) (1msec debounce time default)
Figure 81:
InterruptMask1 Register (Address 74h)
Addr: 74h
InterruptMask1
Bit
Bit Name
Default Access Bit Description
7 LowVsup_int_m
1
6
ovtmp_int_m
1
5
onkey_int_m
1
4
sd5_lv_int_m
1
3
sd4_lv_int_m
1
2
sd3_lv_int_m
1
1
sd2_lv_int_m
1
0
sd1_lv_int_m
1
RW
Set to 0 to enable the interrupt
RW
Set to 0 to enable the interrupt
RW
Set to 0 to enable the interrupt
RW
Set to 0 to enable the interrupt
RW
Set to 0 to enable the interrupt
RW
Set to 0 to enable the interrupt
RW
Set to 0 to enable the interrupt
RW
Set to 0 to enable the interrupt
AS3709 – 60
ams Datasheet, Confidential: 2013-Aug [1-02]