AS3524 Datasheet, PDF (58/124 Pages) General Semiconductor – PASSIVATED ANISOTROPIC RECTIFIER TECHNOLOGY

AS3524 C21 / C22
Data Sheet, Confidential
austriamicrosystems
Table 38 I2S output raw status register
Name
Base
Default
I2SOUT_RAW_STATUS
AS3525_I2SOUT_BASE
0x00
Offset: 0x0008
Bit
Bit Name
7
stereo18_status
6
I2SOUT_POER
5
I2SOUT_PUE
4
I2SOUT_PUAE
3
I2SOUT_PUHF
2
I2SOUT_PUAF
1
I2SOUT_PUF
0
I2SOUT_PUER
Raw status register
The read-only raw status register contains the actual bit values as reflected by the
FIFO controller status signals. I2SOUT_POER and I2SOUT_PUER are static bits,
since FIFO controller gives the PUSH/POP error bit only for one clock. This means
that these two bits remain asserted until they are cleared in the I2SOUT_CLEAR
register. All other bits change state depending on the underlying logic, i.e. state of
FIFO controller.
Default Access
Bit Description
0
R
Status of write interface for 18 bit stereo mode
0: left audio sample is expected next
1: right audio sample is expected next
0
R
1 if FIFO POP error
0
R
1 if FIFO PUSH is empty
0
R
1 if FIFO PUSH is almost empty
0
R
1 if FIFO PUSH is half full
0
R
1 if FIFO PUSH is almost full
0
R
1 if FIFO PUSH is full
0
R
1 if FIFO PUSH error
Table 39 I2S output status register
Name
Base
Default
I2SOUT_STATUS
AS3525_I2SOUT_BASE
0x00
Offset: 0x000C
Bit
Bit Name
7
stereo18_status
6
I2SOUT_POER
5
I2SOUT_PUE
4
I2SOUT_PUAE
3
I2SOUT_PUHF
2
I2SOUT_PUAF
1
I2SOUT_PUF
0
I2SOUT_PUER
Status register
The status register is a read-only register. A read to this register returns the value
of the raw status bits AND’ed with the corresponding mask of enable bits set in the
mask register.
Default Access
Bit Description
0
R
Status of write interface for 18 bit stereo mode
0: left audio sample is expected next
1: right audio sample is expected next
0
R
1 if FIFO POP error
0
R
1 if FIFO PUSH is empty
0
R
1 if FIFO PUSH is almost empty
0
R
1 if FIFO PUSH is half full
0
R
1 if FIFO PUSH is almost full
0
R
1 if FIFO PUSH is full
0
R
1 if FIFO PUSH error
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