TSL208R Datasheet, PDF (3/11 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – 512 x 1 LINEAR SENSOR ARRAY

TSL208R
512 y 1 LINEAR SENSOR ARRAY
TAOS031G − AUGUST 2011
Terminal Functions
TERMINAL
I/O
NAME NO.
DESCRIPTION
AO
4
O Analog output.
CLK
3
I Clock. The clock controls the charge transfer, pixel output and reset.
GND
5
I Ground (substrate). All voltages are referenced to the substrate.
SI
SO
VDD
2
I Serial input. SI defines the start of the data out sequence.
6
O Serial output. SO signals the end of the data out sequence.
1, 7
I Supply voltage for both analog and digital circuits.
lid _{Detailed Description}
a _{The sensor consists of 512 photodiodes arranged in a linear array. Light energy impinging on a photodiode}
v _{generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During}
the integration period, a sampling capacitor connects to the output of the integrator through an analog switch.
ill ^{The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration}
time. The integration time is the interval between two consecutive output periods.
t _{The output and reset of the integrators is controlled by a 512-bit shift register and reset logic. An output cycle}
is initiated by clocking in a logic 1 on SI for one positive going clock edge (see Figures1 and 2)^†. As the SI pulse
G _{s is clocked through the 512-bit shift register, the charge on the sampling capacitor of each pixel is sequentially}
connected to a charge-coupled output amplifier that generates a voltage output, AO. When the bit position goes
A ^t _{low, the pixel integrator is reset. On the 513}th _{clock rising edge, the SI pulse is clocked out of the shift register}
and the output assumes a high-impedance state. Note that this 513^th clock pulse is required to terminate the
s ^{n output of the 512th pixel and return the internal logic to a known state. A subsequent SI pulse can be presented}
as early as the 514^th clock pulse, thereby initiating another pixel output cycle.
m ^{te The voltage developed at analog output (AO) is given by:}
a ⁿ _where:
o _Vout
V_drk
c _Re
E_e
l _tint
V_out = V_drk + (R_e) (E_e) (t_int)
is the analog output voltage for white condition
is the analog output voltage for dark condition
is the device responsivity for a given wavelength of light given in V/(μJ/cm²)
is the incident irradiance in μW/cm²
is integration time in seconds
a _{AO is driven by a source follower with an internal 330-Ω pulldown resistor (no external resistor is required). The}
ic ^{output is nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When}
the device is not in the output phase, AO is in a high impedance state.
n A 0.1 μF bypass capacitor should be connected between V_DD and ground as close as possible to the device.
Tech ^{† For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock.}
Copyright E 2011, TAOS Inc.
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