AS8650A Datasheet, PDF (20/46 Pages) ams AG – High-efficient Power Management Device with High-speed CAN Interface

AS8650A
Datasheet - Detailed Description
7.3 State Diagram
Figure 5. State Machine Model
VSUP_UV_flag = 1 OR V5V_UV_flag =1
 BUS transceiver disabled
 TEMP>Tjwarn
BUS transmitter
disabled BUS transmitter will be
enabled on TEMP < Tjrecv
Normal
Host command (go to ReceiveOnly)
VSUP_UV_flag =1 OR
 V5V_UV_flag= 1 BUS
transceiver disabled
Receive Only
Host command (go to Normal)
Host _{command (go to Normal)}
Host ^{command (go to Sleep)}
Host _{command (go to Standby)}
 TEMP > Tjshut
BUS wake
disabled
From any state
Sleep
Host command (go to Sleep)
TEMP< Tjrecv AND BUS Wake
OR
startuVpLwDaOtc1hOPdRoOgRtimtimeoeuLotuotcal ^Wake
Standby
Power-up
Normal OR
Receive_only OR
Standby state
Power Off
VSUP_POR_RESET ^{== 0}
7.4 Initialization Sequence
The DCDC converter is switched ‘ON’. Subsequently, on receiving power-good (PG) signal from the DCDC converter, the LDO1 regulator is
switched ‘ON’. During the initialization sequence, the VLDO1 is set to 2.5V if VLDO1 > VLDO1_POKTH threshold. VLDO1_RESET is released to
‘high’. Then, active-low PORN_2_OTP is generated.
Initially the rising edge of PORN_2_OTP loads contents into the OTP latch. Next the LOAD_OTP_IN_PREREG signal loads the content of OTP
latch into the pre-regulator domain register. Once the VLDO1_POKTH threshold is reached, the reset timeout timer also starts.
The RESET signal expires after Reset timeout period T_Res. After the RESET signal is ‘high’, the startup watchdog is launched. If the
microcontroller generates a trigger within the startup window, then the device enters into Standby mode.
If the microcontroller fails to generate the trigger, then the RESET signal is generated and the Reset timeout will start.
If the microcontroller fails to generate the startup watchdog trigger for 3 consecutive times, then the device enters into Sleep mode. On receiving
Normal mode command from the microcontroller, the LDO2 and LDO3 regulators are activated. By the time VLDO2 and VLDO3 reach their
respective power-ok (POK) threshold values, an interrupt signal is generated. The AS8650A supports very slow VSUP ramp up of 0.5V/min.
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