AS1524_1 Datasheet, PDF (18/22 Pages) ams AG – 150ksps, 12-Bit, 1-Channel Pseudo/True-Differential and 2-Channel Single-Ended ADCs

AS1524/AS1525
Datasheet - Application Information
Table 6. SSPCON Register Settings
Control Bit
AS1524/AS1525
Setting
Synchronous Serial Port Control Register (SSPCON)
WCOL Bit 7
X
Write Collision Detection Bit
SSPOV Bit 6
SSPEN Bit 5
X
Receive Overflow Detect Bit
Synchronous Serial Port Enable
0: Disables serial port and configures these pins as I/O port pins.
1
1: Enables serial port and configures SCK, SDO, and SCI pins as serial port
pins.
CKP
Bit 4
0
Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
SSPM3:1 Bit 3:1
SSPM0 Bit 0
0
Synchronous Serial Port Mode Select Bit. Sets SPI master mode and
1
selects FCLK = fOSC / 16.
Table 7. SSPSTAT Register Settings
Control Bit
AS1524/AS1525
Setting
Synchronous Serial Status Register (SSPSTAT)
SMP
CKE
Bit 7
Bit 6
0
SPI Data Input Sample Phase. Input data is sampled at the middle of the
data output time.
SPI Clock Edge Select Bit. Data is transmitted on the rising edge of the
1
serial clock.
D/A
Bit 5
X
Data Address Bit
P
Bit 4
X
Stop Bit
S
Bit 3
X
Start Bit
R/W
Bit 2
X
Read/Write Bit Information
UA
Bit 1
X
Update Address
BF
Bit 0
X
Buffer Full Status Bit
www.austriamicrosystems.com
Revision 1.02
18 - 22