AS8202NF_14 Datasheet, PDF (14/25 Pages) ams AG – TTP-C2NF Communication Controller

TTP-C2NF Communication Controller – Data Sheet
AS8202NF
Synchronous READYB Generation
asynchronous READYB
RAM_CLK_TESTSE
15
synchronous READYB
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Figure 5. Synchronous READYB Timing
lid _{Synchronous READYB is aligned to host clock (with pulse duration of one host clock cycle) to}
fulfill the required host timing constraints for input setup and input hold time to/after host clock
a _{rising edge.}
v Note: Connect USE_RAM_CLK to VDD and RAM_CLK_TESTSE to the host processor's bus clock to enable this mode of operation. Due to possible
metastability occurrence, it is not recommended to be used in safety critical systems.
ill ^8.2.
Reset and Oscillator
t _{Pin Name}
G _{s XIN0}
XOUT0
A ^t _XIN1
s ^{n XOUT1}
PLLOFF
e _RESETB
Mode
analog
analog
analog
analog
in
in
Comment
main oscillator input (external clock input)
main oscillator output
bus guardian oscillator input (external clock input)
bus guardian oscillator output
PLL disable
external reset
am ^{nt External Reset Signal}
To issue a reset of the chip the RESETB port has to be driven low for at least 1 us. Pulses
o _{under 50 ns duration are discarded. At power-up the reset must overlap the build-up time of the}
power supply.
l ^c _{Integrated Power-On Reset}
The Device has an internal Power-On Reset generator. When supply voltage ramps up, the
a _{internal reset signal is kept active (low) for 33 µs typical.}
ic _{supply voltage slope}
Parameter
n _{power on reset active time after VDD > 1,0V}
Symbol
dV/dt
tpores
Min
551
25
Typ
-
33
Max
-
49
Unit
V/ms
µs
h ^{Note 1: In case of non-compliance keep the external reset (RESETB) active for min. 5 ms after supply voltage is valid and oscillator inputs active.}
c _{Oscillator Circuitry}
The internal oscillators for main and bus guardian clock require external quartzes or external
e_{oscillators. The main clock features a PLL multiplying a 10 MHz XIN0/XOUT0 oscillation to an}
T^{internal frequency of 40 MHz when enabled.}
Rev. 1.7, Copyright 2000-2007, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
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