AS1358_04 Datasheet, PDF (13/17 Pages) ams AG – 150mA/300mA, Ultra-Low-Noise, High-PSRR Low Dropout Regulators

AS1358 / AS1359
Datasheet - Application Information
9.6.2 Output Capacitor ESR
The series regulator is a negative feedback amplifier, and as such is conditionally stable. The ESR of the output capacitor is usually used to
cancel one of the open loop poles of the error amplifier in order to produce a single pole response. Excessive ESR values may actually cause
instability by excessive changes to the closed loop unity gain frequency crossover point. The range of ESR values for stability is usually shown
either by a plot of stable ESR versus load current, or a limit statement in the datasheet.
Some ceramic capacitors exhibit large capacitance and ESR variations with temperature. Z5U and Y5V capacitors may be required to ensure
stability at temperatures below TAMB = -10ºC. With X7R or X5R capacitors, a 1.0µF capacitor should be sufficient at all operating temperatures.
Larger output capacitor values (2.2µF max) help to reduce noise and improve load transient-response, stability and power-supply rejection.
lid ^{9.6.3 Input Capacitor}
An input capacitor at VIN is required for stability. It is recommended that a 1.0µF capacitor be connected between the AS1358 / AS1359 power
supply input pin VIN and ground (capacitance value may be increased without limit subject to ESR limits). This capacitor must be located at a
distance of not more than 1cm from the VIN pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may
a _{be used at the input.}
v _{9.6.4 Noise}
The regulator output is a DC voltage with noise superimposed on the output. The noise comes from three sources; the reference, the error
ill ^{amplifier input stage, and the output voltage setting resistors. Noise is a random fluctuation and if not minimized in some applications, will}
produce system problems. The AS1358/9 architecture provides enhance noise reduction when an external 10nF capacitor is connected between
Bypass and Output pins, and 1µF connected as the output capacitor.
t _{The leakage current going into the BYPASS pin should be less than 10nA. Increasing the capacitance slightly decreases the output noise.}
G _{s Values above 0.1µF and below 0.001µF are not recommended.}
9.6.5 Transient Response
A ^t _{The series regulator is a negative feedback system, and therefore any change at the output will take a finite time to be corrected by the error}
s ^{n loop. This “propagation time” is related to the bandwidth of the error loop. The initial response to an output transient comes from the output}
capacitance, and during this time, ESR is the dominant mechanism causing voltage transients at the output. More generally:
e _{VTRANSIENT = IOUTPUT  RESR Units are Volts, Amps, Ohms.}
(EQ 14)
m ^{t Thus an initial +50mA change of output current will produce a -12mV transient when the ESR=240m. Remember to keep the ESR within}
stability recommendations when reducing ESR by adding multiple parallel output capacitors.
a ⁿ _{After the initial ESR transient, there follows a voltage droop during the time that the LDO feedback loop takes to respond to the output change.}
o ^{This drift is approximately linear in time and sums with the ESR contribution to make a total transient variation at the output of:}
c V_TRANSIENT
=
I_OUTPUT



R_ES
R
+
-_C----_L--^T_O----_A---_D-_
Units are Volts, Seconds, Farads, Ohms.
(EQ 15)
l _Where:
CLOAD is output capacitor
a _{T = Propagation delay of the LDO}
This shows why it is convenient to increase the output capacitor value for a better support for fast load changes. Of course the formula holds for
ic ^{t < “propagation time”, so that a faster LDO needs a smaller cap at the load to achieve a similar transient response. For instance 50mA load}
current step produces 50mV output drop if the LDO response is 1usec and the load cap is 1µF.
n ^{There is also a steady state error caused by the finite output impedance of the regulator. This is derived from the load regulation specification}
discussed above.
h _{9.6.6 Turn On Time}
c ^{This specification defines the time taken for the LDO to awake from shutdown. The time is measured from the release of the enable pin to the}
time that the output voltage is within 5% of the final value. It assumes that the voltage at VIN is stable and within the regulator Min and Max limits.
e ^{Shutdown reduces the quiescent current to very low, mostly leakage values (<1µA).}
T^{9.6.7 Thermal Protection}
To prevent operation under extreme fault conditions, such as a permanent short circuit at the output, thermal protection is built into the device.
Die temperature is measured, and when a 160ºC threshold is reached, the device enters shutdown. When the die cools sufficiently, the device
will restart (assuming input voltage exists and the device is enabled). Hysteresis of 15ºC prevents low frequency oscillation between start-up and
shutdown around the temperature threshold.
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