AS1310-BTDT-18 Datasheet, PDF (12/20 Pages) ams AG – Ultra Low Quiescent Current, Hysteretic DC-DC Step-Up Converter

AS1310
Datasheet - Detailed Description
8.1.4 Input Capacitor Selection
The input capacitor supports the triangular current during the on-time of the power switch, and maintains a broadly constant input voltage during
this time. The capacitance value is obtained from choosing a ripple voltage during the on-time of the power switch. Additionally, ripple voltage is
generated by the equivalent series resistance (ESR) of the capacitor. For worst case, use maximum peak current values from the datasheet.
C_IN = ^I---^P_V---^E-_R--^A-_I--_PK---_P-^T--_L-^O--_E--^N--
(EQ 15)
Using T_ON = 1µs, and I_PEAK = 480mA, and V_RIPPLE = 50mV, EQ 15 yields:
CIN = 9.6µF
lid ^{Nearest preferred would be 10µF.}
V = I R _{PK _ RIPPLE _ ESR}
PK ESR
(EQ 16)
a _{Typically, the ripple due to ESR is not dominant. ESR for the recommended capacitors (Murata GMR), ESR = 5mΩ to 10mΩ. For the AS1310,}
maximum peak current is 480mA. Ripple due to ESR is 2.4mV to 4.8mV.
v _{Ripple at the input propagates through the common supply connections, and if too high in value can cause problems elsewhere in the system.}
ill ^{The input capacitance is an important component to get right.}
8.1.5 Output Capacitor Selection
t ^{The output capacitor supports the triangular current during the off-time of the power switch (inductor discharge period), and also the load current}
during the wait time (Region D in Figure 13) and on-time (Region A in Figure 13) of the power switch.
AG ^{t s COUT}
=
I _LOAD (T_ON + T_WAIT )
(1− 0.99)V_{OUT _ NOM}
(EQ 17)
s ^{n Note: There is also a ripple component due to the equivalent series resistance (ESR) of the capacitor.}
e _{8.2 Summary}
m ^t _{User Application Defines: VINmin, VINmax, VOUTmin, VOUTmax, ILOADmin, ILOADmax}
a ⁿ _{Inductor Selection:}
o _{Select Max on-time = 0.5µs to 3µs for AS1310. Use (EQ 3) to calculate inductor value.}
Use (EQ 5) to determine off-time.
c _{Use (EQ 6) to check that power delivery matches load requirements assume 70% conversion efficiency.}
l _{Use (EQ 13) to find overall timing period value of T at min VIN and max VOUT for maximum load conditions.}
a _{Input Capacitor Selection: Choose a ripple value and use (EQ 14) to find the value.}
Technic ^{Output Capacitor Selection: Determine TWAIT via (EQ 6) or (EQ 13), and use (EQ 16) to find the value.}
www.austriamicrosystems.com/DC-DC_Step-Up/AS1310
Revision 1.8
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