NSD-2101_07 Datasheet, PDF (11/23 Pages) ams AG – Piezo Motor Driver ASIC for SQL-RV Series Reduced Voltage SQUIGGLE RV and UTAF Motors

NSD-2101
Datasheet - Detailed Description
7.5 Register Map
Table 8 lists out the registers which can be addressed over the I²C interface.
Table 8. I²C Registers
Description
Address
MSB
Data Byte
Note
LSB
Control Register
00h
Period count
01h
lid Pulse count (high byte) 02h
a _{Pulse count (low byte) 03h}
v _{Pulse width}
04h
ill ^{Phase shift}
05h
AG ^{t st} _{Period offset}
06h
amsonten _{Hybrid speed}
07h
Technical ^{c Reserved register}
10h
PS[1] PS[0]
CN[1] CN[0] P1
XXXXXXX
P D DS[1] DS[0]
XX
XXXXXXX
XXXXXXX
XXXXXXX
IDL HB HYB DT
XX
XXXXXXX
XXXXXXX
P2
X
P: Period count MSB;
X
D: Direction bit;
DS: Dead time selection bits: ‘00’=2,
‘01’=4, ‘10’=6 and ‘11’=8 VCO clocks.
X
X
X
CN needs to be 00 to enable Period
offset. Period offset is not used when
either Incremental or Sweep Frequency
Tracking is active.
IDL: Sets idle mode;
HB: Enable half bridge operation if VDD
X
> HB_th;
HYB: Enable hybrid speed control;
DT: Enable signal for increased dead
time;
Selection bits(DS[1:0]) are only valid
when DT=1;
Selection bits should not be changed
when the output driver is active.
Hybrid Speed register: 0… half bridge;
128…full bridge operation; linear
X transition for values in between;
Default: 128. Values from 1 to 127 are
used for linear speed control.
Reserved register used for device test
X only, not accessible during normal
operation.
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Revision 0.6
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