TCS3430 Datasheet, PDF (10/38 Pages) ams AG – The device features advanced digital Ambient Light Sensing

I²C Protocol
TCS3430 − I²C Protocol
The device uses I²C serial communication protocol for
communication. The device supports 7-bit chip addressing and
both standard and full-speed clock frequency modes. Read and
Write transactions comply with the standard set by Philips (now
NXP).
Note(s): The I²C device address can be found in Ordering
Information.
Internal to the device, an 8-bit buffer stores the register address
location of the desired byte to read or write. This buffer
auto-increments upon each byte transfer and is retained
between transaction events (I.e. valid even after the master
issues a STOP command and the I²C bus is released). During
consecutive Read transactions, the future/repeated I²C Read
transaction may omit the memory address byte normally
following the chip address byte; the buffer retains the last
register address +1.
All 16-bit fields have a latching scheme for reading and writing.
In general it is recommended to use I²C bursts whenever
possible, especially in this case when accessing two bytes of
one logical entity. When reading these fields, the low byte must
be read first, and it triggers a 16-bit latch that stores the 16-bit
field. The high byte must be read immediately afterwards. When
writing to these fields, the low byte must be written first,
immediately followed by the high byte. Reading or writing to
these registers without following these requirements will cause
errors.
I²C Write Transaction
A Write transaction consists of a START, CHIP-ADDRESSWRITE,
REGISTER-ADDRESS WRITE, DATA BYTE(S), and STOP. Following
each byte (9TH clock pulse) the slave places an
ACKNOWLEDGE/NOT- ACKNOWLEDGE (ACK/NACK) on the bus.
If NACK is transmitted by the slave, the master may issue a STOP.
I²C Read Transaction
A Read transaction consists of a START, CHIP-ADDRESSWRITE,
REGISTER-ADDRESS, RESTART, CHIP-ADDRESSREAD, DATA
BYTE(S), and STOP. Following all but the final byte the master
places an ACK on the bus (9TH clock pulse). Termination of the
Read transaction is indicated by a NACK being placed on the
bus by the master, followed by STOP.
The I²C bus protocol was developed by Philips (now NXP). For
a complete description of the I²C protocol, please review the
NXP I²C design specification.
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ams Datasheet
[v1-05] 2016-Aug-19