NSD-1202_07 Datasheet, PDF (10/14 Pages) ams AG – Dual Piezo Motor Driver IC for SQL Series SQUIGGLE Motors

NSD-1202
Data Sheet - Detailed Description
7.8 Duty Cycle Register
A register is used to define the duty cycle (or pulse width) of the driver output signal for each motor. The register value is directly transferred to
the analog part.
Since changing the duty cycle will change the speed of the motor, this register can be used to control the speed of two motors independently.
(Motor speed can also be controlled by varying the voltage; however, one setting applies to both motors. See the previous section, Output
Voltage Register.)
To provide motor independent speed control, the duty cycle may be adjusted from 50% (max speed) down to ~12% (minimum speed). A lower
duty cycle could be used, but may not provide enough vibration amplitude to overcome the load.
The default value for this register set during power up or power down (XPD = LOW) is equal to 00h. In this case the default duty cycle of 50% is
lid ^{generated. The resulting duty cycle and resolution of single steps is depending on the master clock frequency and the switching frequency of the}
driver output.
In the following table an example for 20MHz clock input and 150kHz driver frequency is given. The value of the duty cycle register should not
a _{exceed 50% of the period counter value.}
v Duty Cycle Register
0000 0000
ill ^{0000 0001}
0000 1101
t _{0001 1011}
G _{s 0010 1000}
0011 0101
A ^t _{0100 0010}
Technicaaml ^{sconten 01000011}
Min
Typ
Max
Unit
49.6/50.4
%
0.8
%
9.8
%
20.3
%
30.1
%
39.8
%
49.6
%
50.4
%
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