ON33 Datasheet, PDF (1/1 Pages) ams AG – 0.35 UM CMOS

0.35 µm CMOS
ON33
ON33 is an OR / NAND circuit providing the logical function Q = NOT [ (A+B+C).(D+E+F) ].
Truth Table
A BCDE FQ
0 0 0 XXX1
XXX00 0 1
XX1 XX1 0
XX1 X1 X0
XX1 1XX0
X1 XXX1 0
X1 XX1 X0
X1 X1 XX0
1 XXXX1 0
1 XXX1 X0
1 XX1 XX0
Area
0.226 mils²
146 µm²
Capacitance
Pin
Cap [pF]
A
0.018
B
0.018
C
0.018
D
0.017
E
0.016
F
0.015
Power
1.234 µW/MHz
Delay [ns] = tpd.. = f(SL, L)
Output Slope [ns] = op_sl.. = f(SL, L)
with SL = Input Slope [ns] ; L = Output Load [pF]
with L = Output Load [pF]
AC Characteristics: Tj = 25°C VDD = 3.3V Typical Process
AC Characteristics
Slope [ns]
Load [pF]
Delay A => Q
Delay B => Q
Delay C => Q
Delay D => Q
Delay E => Q
Delay F => Q
Slew A => Q
Slew B => Q
Slew C => Q
Slew D => Q
Slew E => Q
Slew F => Q
Rise
0.1
2
0.015 0.15 0.015 0.15
0.29
0.75
0.33
0.76
0.27
0.72
0.39
0.84
0.21
0.66
0.43
0.89
0.23
0.69
0.23
0.7
0.21
0.67
0.3
0.77
0.14
0.61
0.34
0.82
1.09
2.55
1.46
2.72
1.09
2.54
1.51
2.75
1.08
2.54
1.53
2.79
0.99
2.44
1.35
2.61
0.99
2.44
1.41
2.65
0.97
2.45
1.43
2.68
Fall
0.1
2
0.015 0.15 0.015 0.15
0.38
0.79
0.6
1.01
0.34
0.74
0.55
0.97
0.28
0.69
0.47
0.91
0.36
0.77
0.71
1.14
0.32
0.72
0.65
1.1
0.26
0.66
0.56
1.04
0.64
1.56
1.01
1.78
0.54
1.46
0.89
1.68
0.46
1.37
0.79
1.58
0.65
1.56
1.1
1.87
0.55
1.47
0.98
1.77
0.45
1.36
0.84
1.67
April 2000
Page 1 of 1
Rev. N/C