ATXMEGA128B1 Datasheet, PDF (65/138 Pages) ATMEL Corporation – 8/16-bit Atmel XMEGA B1 Microcontroller

Mnemonics
SEV
CLV
SET
CLT
SEH
CLH
BREAK
NOP
SLEEP
WDR
Operands
Description
Set Two’s Complement Overflow
Clear Two’s Complement Overflow
Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
Break
No Operation
Sleep
Watchdog Reset
Operation
V1
V0
T1
T0
H1
H0
MCU control instructions
(See specific descr. for BREAK)
(see specific descr. for Sleep)
(see specific descr. for WDR)
Flags
V
V
T
T
H
H
None
None
None
None
Notes:
1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface.
2. One extra cycle must be added when accessing Internal SRAM.
#Clocks
1
1
1
1
1
1
1
1
1
1
XMEGA B1 [DATASHEET] 65
8330C–AVR–07/2012