FCCSP Datasheet, PDF (1/2 Pages) Amkor Technology – a flip chip solution in a CSP package format.

data sheet
L A M I N AT E
fcCSP Packages:
Amkor Technology is now offering the Flip Chip CSP
(fcCSP) package — a flip chip solution in a CSP
package format. This package construction utilizes
eutectic tin/lead (63Sn/37Pb) flip chip interconnect
technology, in either area array or peripheral bump
layout, replacing standard wirebond interconnect. The
advantages of flip chip interconnect are twofold: it
provides enhanced electrical performance over
standard wirebond technology, and it allows for a
smaller form factor due to increased routing density,
the ability to use area array die bumps and the
elimination of wirebond loops. Current wafer bump
technology and flip chip assembly process allows for a
minimum of 150 µm peripheral flip chip bumping, or
250 µm area array bumping.
The fcCSP is based on Amkor's proprietary
ChipArray^® BGA (CABGA) package construction,
using cutting edge thin core laminate substrates.
The package is assembled in strip format, gang
molded and saw singulated for manufacturing
efficiency and cost minimization. Laser ablated solder
mask technology, via-in-pad substrate structure, and
thin core substrate panel processing allow for
increased routing density and enhanced electrical
performance, making the fcCSP an attractive option
for advanced CSP applications where electrical
performance is a critical factor.
The fcCSP is available in both thin core laminate
substrate technology, as well as ceramic substrate
technology. Package size ranges from 3 mm to 15
mm, accommodating BGA ball pitches from 0.5 mm
to 1.0 mm. In addition to BGA technology, the fcCSP
is also available in LGA format, allowing for a lower
minimum package thickness.
The Ceramic flip chip package provides maximum
flexibility for designers for number of layers and
routing. Current production is from 300 - 1800 I/O
in LGA, BGA or SCI (solder column interposer)
formats, 1.27 mm and 1.0 mm pitch. AlSiC lids
can be attached for maximum thermal dissipation.
fcCSP
Features:
• Designed for high frequency applications
• 49 - 1800 ball counts
• Target Market - Cell Phones, Hand-held Electronics
• Thin core laminate or ceramic package construction
• Overmolded for handling and second level reliability
• Accommodates package sizes from 3 mm to 15 mm
• Flip Chip bump pitches of 150 µm min. for
peripheral array, 250 µm min. for area array
• Available in 0.5 mm - 1.0 mm BGA ball pitch,
as well as LGA interconnect
• Minimum nominal package thickness of 0.80 mm for
LGA interconnect, 1.0 mm for 0.5 mm BGA pitch,
1.2 mm for 0.8 mm pitch
• Turnkey Solution - Design, bumping, bumped wafer
probe, backgrind, assembly, test
• Much better signal to noise ratio at higher
frequencies (>1Ghz)
• Low inductance of flip chip bumps - short, direct
signal path
• Flexible customized substrate routing
Thermal Performance:
Theta JA (°CW)
• 8 x 8 mm, 64 lead package with
1.75 mm x 2.27 mm die, 0.8 mm pitch,
0.6 mm mold cap
• 0 LFPM, 4 layer PC board
• Junction ambient thermal resistance = 48.1 °C/W
Electrical:
8 x 8 mm body, 64 ld, 0.8 mm ball pitch
Inductance
Min
0.26 nH
Max
2.16 nH
Capacitance
0.18 pF
0.38 pF
Resistance
7 mΩ
53.9 mΩ
Simulated results @ at 100 MHz
Reliability:
Package Level:
• Laminate Moisture
Sensitivity
• Ceramic Moisture
Sensitivity
• PCT
• Temp/Humidity
• High temp storage
• Temp cycle
JEDEC Level 3 @ 240 °C
30 °C/60% RH, 192 hours
JEDEC Level 1 @ 260 °C
85 °C/85% RH, 168 hours
121 °C/100% RH, 96 hours
85 °C/85% RH, 1000 hours
150 °C, 1000 hours
-55 °C/+125 °C, 1000 cycles
Board Level:
• Thermal cycle
• Thermal cycle
-40 °C/+125 °C,
1 cycle/hour, 3000 cycles*
-40 °C/+125 °C,
2 cycles/hour, 2500 cycles*
*Data for 8 x 8 mm body, 64 lead, 0.33 mm PWB NSMD pad size
VISIT AMKOR TECHNOLOGY ONLINE FOR LOCATIONS AND
TO VIEW THE MOST CURRENT PRODUCT INFORMATION.
w w w. a m ko r. c o m
DS577D
Rev Date: 07’05