A48P4616B Datasheet, PDF (9/66 Pages) AMIC Technology – 16M X 16 Bit DDR DRAM

A48P4616B
Operating Mode
The normal operating mode is selected by issuing a Mode
Register Set Command with bits A7-A12 to zero, and bits A0-
A6 set to the desired values. A DLL reset is initiated by
issuing a Mode Register Set command with bits A7 and A9-
A12 each set to zero, bit A8 set to one, and bits A0-A6 set to
the desired values. A Mode Register Set command issued to
reset the DLL should always be followed by a Mode Register
Set command to select normal operating mode.
All other combinations of values for A7-A12 are reserved for
future use and/or test modes. Test modes and reserved
states should not be used as unknown operation or
incompatibility with future versions may result.
CAS Latencies
CK
CK
Command
DQS
CAS Latency = 2, BL = 4
Read
NOP
CL=2
NOP
NOP
NOP
NOP
DQ
CK
CK
Command
DQS
DQ
CAS Latency = 2.5, BL = 4
Read
NOP
CL=2.5
NOP
NOP
NOP
NOP
CK
CK
Command
DQS
DQ
Read
NOP
NOP
CL=3
Shown with nominal tAC, tDQSCK and tDQSQ
CAS Latency = 3, BL = 4
NOP
NOP
NOP
: Don't care
(January, 2014, Version 1.0)
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AMIC Technology, Corp.