A26E001A Datasheet, PDF (9/14 Pages) AMIC Technology – 2M and 256K MaskRAM

Timing Waveforms (SRAM Selected continued)
Read Cycle 3 ^{(1, 3, 4)}
RAMCE
D OUT
tCLZ ⁵
tACE
A26E001A
tCHZ ⁵
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled, RAMCE = VIL.
3. Address valid prior to or coincident with RAMCE transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
Write Cycle 1⁽⁶⁾
(Write Enable Controlled)
Address
RAMCE
WE
D IN
D OUT
(4)
tAS1
tWC
tAW
tCW ⁵
tWP2
tWR ³
tDW
tWHZ ⁷
tDH
tOW ⁷
(November, 1998, Version 2.1)
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AMIC Technology, Inc.