LP62S16128B-I_15 Datasheet, PDF (8/14 Pages) AMIC Technology – 128K X 16 BIT LOW VOLTAGE CMOS SRAM

Timing Waveforms
Read Cycle 1^{(1, 2, 4)}
Address
DOUT
tRC
tAA
tOH
LP62S16128B-I Series
tOH
Read Cycle 2^{(1, 2, 3)}
Address
CE
HB, LB
OE
DOUT
tRC
tAA
tCLZ⁵
tACE
tBE
tBLZ⁵
tOE
tOLZ⁵
tCHZ⁵
tBHZ⁵
tOHZ⁵
Notes:
1. WE is high for Read Cycle.
2. Device is continuously enabled CE = VIL, HB = VIL and, or LB = VIL.
3. Address valid prior to or coincident with CE and ( HB and, or LB ) transition low.
4. OE = VIL.
5. Transition is measured ±500Mv from steady state. This parameter is sampled and not 100% tested.
(June, 2004, Version 1.4)
7
AMIC Technology, Corp.