ASR8600 Datasheet, PDF (7/14 Pages) AMIC Technology – Ambient Light, Solar-UV, IR and Proximity Sensor

ASR8600
I2C Protocol
The bus interface and control are accomplished through an
I2C compatible, 2-wire serial interface consisting of a
serial-data line (SDA) and a serial-clock line (SCL). SDA and
SCL facilitate communication between the IC and the master
at clock rate up to 400k Hz. The devices support the 7-bit I2C
addressing protocol and 8-bit register address and data byte.
The I2C standard provides for three types of bus transaction:
read, write, and a combined protocol.
During a write operation, after (slave_address + R/W) byte,
the first byte written is a register address followed by data
byte. If a read command is issued, the register address from
the previous command will be used for data access. In a
combined protocol, the first byte written is the register
address followed by reading a series of data bytes.
ASR8600 slave address is 1001010X, which 0x94 is Write to
ASR8600, and 0x95 is Read from ASR8600.
The I2C bus protocol follows Philip^TM (now NXP company)
I2C specification. For a complete description of I2C protocol,
please refer to NXP I2C design specification.
I2C Protocols
1
7
11
8
1
S Slave Address W A Register Address A
8
Data Byte
11
A ^... P
I2C Write Protocol
1
7
11
8
1
S Slave Address R A
Data Byte
A
8
Data Byte
11
A ^... P
I2C Read Protocol
1
7
11
8
1
S Slave Address W A Register Address A SR
8
Data Byte
1
A ^...
8
Data Byte
1
A ^...
7
Slave Address
8
Data Byte
11
RA
11
NP
I2C Read Protocol - Combined Format
A Acknowledge (0)
N Not Acknowledge (1)
P Stop Condition
R Read (1)
S Start Condition
SR Repeated Start Condition
W_...
Write (0)
Condition of protocol
Master-to-Slave
Slave-to-Master
Timing Diagrams
SCL
t(LOW)
VIH
VIL
t(R)
t(HDSTA)
t(BUF)
SDA
t(HDDAT)
VIH
VIL
P
S
Stop Start
Condition Condition
t(F)
t(HIGH) t(SUSTA)
t(SUDAT)
S
t(SUSTO)
P
I2C Bus Timing Characteristics
Symbol
f_(SCL)
t_(HIGH)
t_(LOW)
T_(R)
T_(F)
t_(SUDAT)
t_(HDDAT)
t_(BUF)
t_(HDSTA)
t_(SUSTA)
t_(SUSTO)
t_(SP)
Parameter
Serial-Clock Frequency
Clock High Period
Clock Low Period
Clock/Data Rise Time
Clock/Data Fall Time
Data Setup Time
Data Hold Time
Bus Free Time Between STOP and START
Hold Time (Repeated) Start Condition
Repeated Start Condition Setup Time
Stop Condition Setup Time
Pulse Width of Suppressed Spike
PRELIMINARY (March, 2015, Version 0.0)
6
Min.
0
0.6
1.3
0.1
0
1.3
0.6
0.6
0.6
0
Typ.
100
100
Max.
Unit
400
KHz
µs
µs
ns
ns
µs
µs
µs
µs
µs
µs
50
ns
AMIC Technology Corp.