A25LMQ64 Datasheet, PDF (39/70 Pages) AMIC Technology – 64M-BIT (x1 / x2 / x4) 3.3V CMOS MXSMIO

A25LMQ64 Series
Table 12. AC Characteristics (TA = -40°C to 125°C, VCC = 2.7V ~ 3.6V)
Symbol
fC
Alt.
Parameter
Clock Frequency for the following instructions: FAST READ, PP,
fC 4PP, SE, BE, CE, DP, RES, RDP WREN, WRDI, RDID, RDSR,
WRSR
Min. Typ. Max. Unit
D.C.
104 MHz
fRC
fR Clock Frequency for READ instructions
fT Clock Frequency for 2READ instructions
fTC
fQ Clock Frequency for 4READ instructions ⁽⁵⁾
tCH⁽¹⁾⁽²⁾
tCLH Clock High Time
Serial (fC)
4.5
4PP and Normal Read (fRC)
4.5
tCL⁽¹⁾⁽²⁾
tCLL Clock Low Time
Serial (fC)
4.5
4PP and Normal Read (fRC)
4.5
tCLCH⁽²⁾
Clock Rise Time ⁽³⁾ (peak to peak)
0.1
tCHCL⁽²⁾
Clock Fall Time ⁽³⁾ (peak to peak)
0.1
tSLCH⁽²⁾
tCSS _S Active Setup Time (relative to C)
4
tCHSL⁽²⁾
S Not Active Hold Time (relative to C)
4
tDVCH
tDSU Data In Setup Time
2
tCHDX⁽²⁾
tDH Data In Hold Time
3
tCHSH
S Active Hold Time (relative to C)
5
tSHCH
S Not Active Setup Time (relative to C)
5
tSHSL⁽³⁾
tCSH _S Deselect Time
Read
Write/Erase/Program
10
30
tSHQZ ⁽²⁾
tDIS Output Disable Time
66 MHz
84 MHz
84 MHz
ns
ns
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
8
ns
tCLQV
tV
Clock Low to Output Valid
Loading: 30pF/15pF
Loading: 30pF
Loading: 15pF
tCLQX
tHO Output Hold Time
0
tWHSL
Write Protect Setup Time
20
tSHWL
tDP⁽²⁾
tRES1⁽²⁾
Write Protect Hold Time
100
S High to Deep Power-down Mode
S High to Standby Mode without Electronic Signature Read
tRES2⁽²⁾
S High to Standby Mode with Electronic Signature Read
10
ns
8
ns
ns
ns
ns
10
μs
10
μs
10
μs
tRCR
Recovery Time from Read
tRCP
Recovery Time from Program
20
μs
20
μs
tRCE
tW
tBP
tPP
tSE
tBE32
Recovery Time from Erase
Write Status Register Cycle Time
Byte-Program
Page Program Cycle Time
Sector Erase Cycle Time
Block Erase (32KB) Cycle Time
12
ms
120 ms
6
30
μs
0.35
3
ms
40
150 ms
80
300 ms
tBE
Block Erase (64KB) Cycle Time
tCE
Chip Erase Cycle Time
120 500 ms
12
25
s
Notes:
1. tCH + tCL must be greater than or equal to 1/ Frequency.
2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
4. Test condition is shown as Figure 11.
5. When dummy cycle=4 (In both QPI & SPI mode), clock rate=84MHz; when dummy cycle=6 (In both QPI & SPI mode), clock
rate=84MHz.
PRELIMINARY (August, 2014, Version 0.2)
38
AMIC Technology Corp.