A43L0616B Datasheet, PDF (38/45 Pages) AMIC Technology – 512K X 16 Bit X 2 Banks Synchronous DRAM

Active/Precharge Power Down Mode @CAS Lantency=2, Burst Length=4
A43L0616B
0
CLOCK
CKE
CS
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
tSS
* Note 1
* Note 2
tSS
tSS
tSS
*Note 3
RAS
CAS
ADDR
Ra
Ca
BA
A10/AP
Ra
WE
DQM
DQ
Qa0 Qa1 Qa2
Precharge
Power-down
Entry
Precharge
Power-down
Exit
Row Active
Active
Power-down
Entry
Read
Active
Power-down
Exit
Precharge
: Don't care
* Note : 1. All banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least “1CLK + tSS” prior to Row active command.
3. Cannot violate minimum refresh specification. (32ms)
PRELIMINARY (May, 2005, Version 0.0)
37
AMIC Technology, Corp.