A43L2632 Datasheet, PDF (37/43 Pages) AMIC Technology – 1M X 32 Bit X 4 Banks Synchronous DRAM

A43L2632
Self Refresh Entry & Exit Cycle
0
CLOCK
CKE
CS
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
* Note 2
* Note 1
tSS
* Note 3
* Note 4
tSS
tRC
min. _{* Note 6}
* Note 5
RAS
* Note 7
CAS
* Note 7
ADDR
BS0, BS1
A10/AP
WE
DQM
DQ
Hi-Z
Hi-Z
Self Refresh Entry
Self Refresh Exit
Auto Refresh
: Don't care
* Note : TO ENTER SELF REFRESH MODE
1. CS, RAS & CAS and CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
(cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit.
If the system uses burst refresh.
PRELIMINARY (January, 2005, Version 0.0)
36
AMIC Technology, Corp.