A25LQ64 Datasheet, PDF (34/70 Pages) AMIC Technology – 64M-BIT (x1 / x2 / x4) 3.3V CMOS MXSMIO

A25LQ64 Series
Program/Erase Suspend/Resume
The device allow the interruption of Sector-Erase, Block-Erase
or Page-Program operations and conduct other operations.
Details as follows.
To enter the suspend/resume mode: issuing B0h for suspend;
30h for resume (SPI/QPI all acceptable)
Read security register bit2 (PSB) and bit3 (ESB) (please refer
to table 11 to check suspend ready information.
Suspend to suspend ready timing: 20μs.
Resume to another suspend timing: 1ms.
ESB bit (Erase Suspend Bit) indicates the status of Erase
suspend operation. When issue a suspend command during
erase operation ESB=1, when erase operation resumes, ESB
will be reset to "0".
Both SPI (8 clocks) and QPI (2 clocks) command cycle can
accept by this instruction. The IO[3:1] are don't care when
during SPI mode.
Erase Suspend
Erase suspend allow the interruption of all erase operations.
After erase suspend, WEL bit will be clear, only read related,
resume and reset command can be accepted unconditionally.
(including: 03h, 0Bh, 3Bh, BBh, EBh, E7h, 9Fh, AFh, 90h, 05h,
2Bh, B1h, C1h, 5Ah, 3Ch, 30h, 66h, 99h, C0h, 35h, F5h, 00h,
ABh)
For erase suspend to program operation, the programming
command (38, 02) can be accepted under conditions as
follows:
The block group (BG) is divided into 32BGs in this device,
each BG's density is 2Mb. While conducting erase suspend in
one BG, the programming operation that follows can only be
conducted in one of the other BGs and should not be
conducted in the BG executing the suspend operation. The
boundaries of the BGs are illustrated as below table.
BG (2M bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Address Range
7C0000h-7FFFFFh
780000h-7BFFFFh
740000h-77FFFFh
700000h-73FFFFh
6C0000h-6FFFFFh
680000h-6BFFFFh
640000h-67FFFFh
600000h-63FFFFh
5C0000h-5FFFFFh
580000h-5BFFFFh
540000h-57FFFFh
500000h-53FFFFh
4C0000h-4FFFFFh
480000h-4BFFFFh
440000h-47FFFFh
400000h-43FFFFh
BG (2M bit)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Address Range
3C0000h-3FFFFFh
380000h-3BFFFFh
340000h-37FFFFh
300000h-33FFFFh
2C0000h-2FFFFFh
280000h-2BFFFFh
240000h-27FFFFh
200000h-23FFFFh
1C0000h-1FFFFFh
180000h-1BFFFFh
140000h-17FFFFh
100000h-13FFFFh
0C0000h-0FFFFFh
080000h-0BFFFFh
040000h-07FFFFh
000000h-03FFFFh
After issue erase suspend command, latency time 20μs is
needed before issue another command. For "Suspend to
Read", "Resume to Read", "Resume to Suspend" timing
specification please note Figure 41-1, Figure 41-2 and Figure
41-3.
ESB bit (Erase Suspend Bit) indicates the status of Erase
suspend operation. When issue a suspend command during
program operation ESB=1, when erase operation resumes,
ESB will be reset to "0".
Both SPI (8 clocks) and QPI (2 clocks) command cycle can
accept by this instruction. The IO[3:1] are don't care when
during SPI mode.
When ESB bit is issued, the Write Enable Latch (WEL) bit will
be reset.
See Figure 41-1 for Suspend to Read latency.
(July, 2014, Version 1.4)
33
AMIC Technology Corp.