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A25L20P Datasheet, PDF (33/43 Pages) AMIC Technology – 2Mbit / 1Mbit / 512Kbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface
A25L20P/A25L10P/A25L05P Series
Table 16. AC Characteristics
Symbol
Alt.
Parameter
fC
fR
tCH 1
tCL 1
tCLCH 2
tCHCL 2
tSLCH
fC
Clock Frequency for the following instructions: FAST_READ,
PP, SE, BE, DP, RES, RDID, WREN, WRDI, RDSR, WRSR
Clock Frequency for READ instructions
tCLH Clock High Time
tCLL Clock Low Time
Clock Rise Time3 (peak to peak)
Clock Fall Time3 (peak to peak)
tCSS
S Active Setup Time (relative to C)
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
tSHQZ 2
tCLQV
tCLQX
tHLCH
S Not Active Hold Time (relative to C)
tDSU Data In Setup Time
tDH Data In Hold Time
S Active Hold Time (relative to C)
S Not Active Setup Time (relative to C)
tCSH
S Deselect Time
tDIS Output Disable Time
tV
Clock Low to Output Valid
tHO Output Hold Time
HOLD Setup Time (relative to C)
tCHHH
HOLD Hold Time (relative to C)
tHHCH
tCHHL
tHHQX 2
tHLQZ 2
tWHSL 4
tSHWL 4
tDP 2
tRES1 2
tRES2 2
tW
tpp
tSE
tBE
HOLD Setup Time (relative to C)
HOLD Hold Time (relative to C)
tLZ
HOLD to Output Low-Z
tHZ
HOLD to Output High-Z
Write Protect Setup Time
Write Protect Hold Time
S High to Deep Power-down Mode
S High to Standby Mode without Electronic Signature Read
S High to Standby Mode with Electronic Signature Read
Write Status Register Cycle Time
Page Program Cycle Time
Sector Erase Cycle Time
Bulk Erase Cycle Time of A25L20P
Bulk Erase Cycle Time of A25L10P
Bulk Erase Cycle Time of A25L05P
Note: 1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
Min.
D.C.
D.C.
6
5
0.1
0.1
5
5
5
5
5
5
100
0
5
5
5
5
20
100
Typ.
100
3
1
6
4
3
Max.
85
50
8
8
8
8
3
30
30
300
5
3
8
6
5
Unit
MHz
MHz
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
ms
ms
s
s
s
s
(August, 2007, Version 1.0)
32
AMIC Technology Corp.