AD7485 Datasheet, PDF (3/16 Pages) AMIC Technology – 1 MSPS, Serial 14-Bit SAR ADC

AD7485
Parameter
Specification
Unit
Test Conditions/Comments
POWER REQUIREMENTS
V_DD
V_DRIVE
5
V
± 5%
2.7
V min
5.25
V max
I_DD
Normal Mode (Static)
12
mA max
Normal Mode (Operational)
16
mA max
NAP Mode
0.6
mA max
STANDBY Mode⁸
2
µA max
0.5
µA typ
Power Dissipation
Normal Mode (Operational)
80
mW max
NAP Mode
3
mW max
STANDBY Mode⁸
10
µW max
NOTES
1_{Temperature ranges as follows: –40°C to +85°C.}
2_{SINAD figures quoted include external analog input circuit noise contribution of approximately 1 dB.}
3_{See Typical Performance Characteristics section for analog input circuits used.}
4_{See Terminology.}
5_{Sample tested @ 25°C to ensure compliance.}
6_{Current drawn from external reference during conversion.}
7_{ILOAD = 200 µA.}
8_{Digital input levels at GND or VDRIVE.}
Specifications subject to change without notice.
TIMING CHARACTERISTICS1 (VDD = 5 V ؎ 5%, AGND = DGND = 0 V, VREF = External; all specifications TMIN to TMAX and
valid for V_DRIVE = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter
Symbol
Min
Typ
Max
Unit
Master Clock Frequency
MCLK Period
Conversion Time
CONVST Low Period (Mode 1)²
CONVST High Period (Mode 1)²
MCLK High Period
MCLK Low Period
CONVST Falling Edge to MCLK Rising Edge
MCLK Rising Edge to MSB Valid
Data Valid before SCO Falling Edge
Data Valid after SCO Falling Edge
CONVST Rising Edge to SDO Three-State
CONVST Low Period (Mode 2)²
CONVST High Period (Mode 2)³
CONVST Falling Edge to TFS Falling Edge
TFS Falling Edge to MSB Valid
TFS Rising Edge to SDO Three-State
TFS Low Period⁴
TFS High Period⁴
MCLK Fall Time
MCLK Rise Time
MCLK – SCO Delay
f_MCLK
t₁
t₂
t₃
t₄
t₅
t₆
t₇
t₈
t₉
t₁₀
t₁₁
t₁₂
t₁₃
t₁₄
t₁₅
t₁₆
t₁₇
t₁₈
t₁₉
t₂₀
t₂₁
0.01
40
t₁ Ï« 24
t₁ Ï« 22
10
0.4 Ï« t₁
0.4 Ï« t₁
7
10
20
10
10
10
t₁ Ï« 22
10
5
5
6
25
100000
0.6 Ï« t₁
0.6 Ï« t₁
15
6
t₁ Ï« 2
30
8
25
25
25
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1_{All timing specifications given above are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used.}
2_{CONVST idling high. See Serial Interface section for further details.}
3_{CONVST idling low. See Serial Interface section for further details.}
4_{TFS can also be tied low in this mode.}
Specifications subject to change without notice.
REV. 0
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