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A43L2616 Datasheet, PDF (29/41 Pages) AMIC Technology – 1M X 16 Bit X 4 Banks Synchronous DRAM
Read & Write Cycle at Different Bank @Burst Length=4
A43L2616
0
CLOCK
CKE
CS
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
High
RAS
CAS
ADDR
RAa
CAa
BS1
BS0
A10/AP
RAa
WE
RDb
RDb
CDb RBc
CBc
RBC
tCDL
*Note 1
DQM
DQ
(CL=2)
DQ
(CL=3)
QAa0 QAa1 QAa2 QAa3
QAa0 QAa1 QAa2 QAa3
DDb0 DDb1 DDb2 DDb3
DDb0 DDb1 DDb2 DDb3
QBc0 QBc1 QBc2
QBc0 QBc1
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(D-Bank)
* Note : tCDL should be met to complete write.
Write
(D-Bank)
Row Active
(B-Bank)
Read
(B-Bank)
: Don't care
(September, 2004, Version 3.1)
28
AMIC Technology, Corp.