A25L016_15 Datasheet, PDF (29/43 Pages) AMIC Technology – 16Mbit Low Voltage, Serial Flash Memory

POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must not be
selected (that is Chip Select ( ^S ) must follow the voltage
applied on V_CC) until V_CC reaches the correct value:
­ V_CC (min) at Power-up, and then for a further delay of t_VSL
­ V_SS at Power-down
Usually a simple pull-up resistor on Chip Select ( ^S ) can be
used to insure safe and proper Power-up and Power-down.
To avoid data corruption and inadvertent write operations
during power up, a Power On Reset (POR) circuit is included.
The logic inside the device is held reset while V_CC is less than
the POR threshold value, V_WI – all operations are disabled,
and the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page
Program (PP), Sector Erase (SE), Block Erase (BE), Chip
Erase (CE) and Write Status Register (WRSR) instructions
until a time delay of t_PUW has elapsed after the moment that
V_CC rises above the VWI threshold. However, the correct
operation of the device is not guaranteed if, by this time, V_CC
is still below V_CC(min). No Write Status Register, Program or
Erase instructions should be sent until the later of:
A25L016 Series
­ t_PUW after V_CC passed the VWI threshold
- t_VSL afterV_CC passed the V_CC(min) level
These values are specified in Table 8.
If the delay, t_VSL, has elapsed, after V_CC has risen above
V_CC(min), the device can be selected for READ instructions
even if the t_PUW delay is not yet fully elapsed.
At Power-up, the device is in the following state:
­ The device is in the Standby mode (not the Deep
Power-down mode).
­ The Write Enable Latch (WEL) bit is reset.
Normal precautions must be taken for supply rail decoupling,
to stabilize the V_CC feed. Each device in a system should
have the V_CC rail decoupled by a suitable capacitor close to
the package pins. (Generally, this capacitor is of the order of
0.1µF).
At Power-down, when V_CC drops from the operating voltage,
to below the POR threshold value, V_WI, all operations are
disabled and the device does not respond to any instruction.
(The designer needs to be aware that if a Power-down occurs
while a Write, Program or Erase cycle is in progress, some
data corruption can result.)
Figure 21. Power-up Timing
V_CC
V_CC(max)
V_CC(min)
t_PU
Full Device Access
time
(March, 2012, Version 2.0)
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AMIC Technology Corp.