A43L4616A Datasheet, PDF (28/43 Pages) AMIC Technology – 4M X 16 Bit X 4 Banks Synchronous DRAM

Page Read Cycle at Different Bank @Burst Length = 4
A43L4616A
0
CLOCK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CKE
*Note 1
CS
High
RAS
CAS
*Note 2
ADDR
RAa
RBb CAa
RCc CBb
RDd CCc
CDd
BS1
BS0
A10/AP
RAa
RBb
WE
DQM
DQ
(CL=2)
DQ
(CL=3)
RCc
RDd
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
Row Active
(A-Bank)
Read
(A-Bank)
Row Active
(B-Bank)
Read
(B-Bank)
Read
(C-Bank)
Row Active
(D-Bank)
Row Active
(C-Bank)
Precharge
(A-Bank)
Precharge
(B-Bank)
Read
(D-Bank)
Precharge
(C-Bank)
Precharge
(D-Bank)
: Don't care
* Note : 1. CS can be don’t care when RAS, CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read ad the precharge banks must be the same.
PRELIMINARY (May, 2010, Version 0.4)
27
AMIC Technology, Corp.