A43L2616A Datasheet, PDF (28/42 Pages) AMIC Technology – 1M X 16 Bit X 4 Banks Synchronous DRAM

Page Write Cycle at Different Bank @Burst Length=4
A43L2616A
0
CLOCK
CKE
CS
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
High
RAS
CAS
ADDR
RAa
BS1
BS0
A10/AP
RAa
DQ
WE
DQM
RBb CAa
CBb RCc
RDd CCc
CDd
*Note 2
RBb
RCc
RDd
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DCc0 DCc1 DDd0 DDd1 CDd2
tCDL
tRDL
*Note 1
Row Active
(A-Bank)
Write
(A-Bank)
Row Active
(B-Bank)
Write
(B-Bank)
Row Active
(D-Bank)
Row Active
(C-Bank)
Write
(C-Bank)
Write
(D-Bank)
Precharge
(All Banks)
: Don't care
* Note:
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and precharge banks must be the same.
PRELIMINARY (November, 2004, Version 0.0)
27
AMIC Technology, Corp.