A43L3616A Datasheet, PDF (26/41 Pages) AMIC Technology – 2M x 16 Bit x 4 Banks Synchronous DRAM

Page Read & Write Cycle at Same Bank @Burst Length=4
A43L3616A Series
0
CLOCK
CKE
CS
RAS
CAS
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
High
tRCD
*Note 2
ADDR
Ra
Ca0
Cb0
Cc0
Cd0
BA0
BA1
A10/AP
Ra
WE
DQM
DQ
(CL=2)
*Note 2
*Note1
tCDL
tRDL
*Note3
Qa0 Qa1 Qb0 Qb1
Dc0 Dc1 Dd0 Dd1
DQ
(CL=3)
Qa0 Qa1 Qb0
Dc0 Dc1 Dd0 Dd1
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write
command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
: Don't care
PRELIMINARY (November, 2011, Version 0.8)
25
AMIC Technology, Corp.