A25P020 Datasheet, PDF (23/45 Pages) AMIC Technology – 2Mbit Low Voltage, Serial Flash Memory

A25P020 Series
Chip Erase (CE)
The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before
it can be accepted, a Write Enable (WREN) instruction must
previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL).
The Chip Erase (CE) instruction is entered by driving Chip
Select ( ^S ) Low, followed by the instruction code on Serial
Data Input (DIO). Chip Select ( ^S ) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 15. Chip Select
( ^S ) must be driven High after the eighth bit of the instruction
code has been latched in, otherwise the Chip Erase
Figure 15. Chip Erase (CE) Instruction Sequence
instruction is not executed. As soon as Chip Select ( ^S ) is
driven High, the self-timed Chip Erase cycle (whose duration
is t_CE) is initiated. While the Chip Erase cycle is in progress,
the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is
1 during the self-timed Chip Erase cycle, and is 0 when it is
completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Chip Erase (CE) instruction is executed only if all Block
/Sector Protect (SEC, BP2, BP1, BP0) bits are 0. The Chip
Erase (CE) instruction is ignored if one, or more, blocks are
protected.
S
01 2 3 45 67
C
Instruction
(C7h or 60h)
DIO
PRELIMINARY (November, 2014, Version 0.2)
22
AMIC Technology Corp.