A45L9332A Datasheet, PDF (17/55 Pages) AMIC Technology – 256K X 32 Bit X 2 Banks Synchronous Graphic RAM

A45L9332A Series
Device Operations (continued)
command is asserted. The maximum time any bank can be
active is specified by tRAS(max). Therefore, each bank has
to be precharged within tRAS(max) from the bank activate
command. At the end of precharge, the bank enters the idle
state and is ready to be activated again.
Entry to Power Down, Auto refresh, Self refresh and Mode
register Set etc, is possible only when both banks are in
idle state.
Auto Precharge
The precharge operation can also be performed by using
auto precharge. The SGRAM internally generates the
timing to satisfy tRAS(min) and “tRP” for the programmed
burst length and CAS latency. The auto precharge
command is issued at the same time as burst read or burst
write by asserting high on A9. If burst read or burst write
command is issued with low on A9, the bank is left active
until a new command is asserted. Once auto precharge
command is given, no new commands are possible to that
particular bank until the bank achieves idle state.
Both Banks Precharge
Both banks can be precharged at the same time by using
Precharge all command. Asserting low on CS , RAS and
WE with high on A9 after both banks have satisfied
tRAS(min) requirement, performs precharge on both banks.
At the end of tRP after performing precharge all, both banks
are in idle state.
Auto Refresh
The storage cells of SGRAM need to be refreshed every
32ms to maintain data. An auto refresh cycle accomplishes
refresh of a single row of storage cells. The internal counter
increments automatically on every auto refresh cycle to
refresh all the rows. An auto refresh command is issued by
asserting low on CS , RAS and CAS with high on CKE
and WE . The auto refresh command can only be asserted
with both banks being in idle state and the device is not in
power down mode (CKE is high in the previous cycle). The
time required to complete the auto refresh operation is
specified by “tRC(min)”. The minimum number of clock
cycles required can be calculated by driving “tRC” with clock
cycle time and then rounding up to the next higher integer.
The auto refresh command must be followed by NOP’s until
the auto refresh operation is completed. Both banks will be
in the idle state at the end of auto refresh operation. The
auto refresh is the preferred refresh mode when the
SGRAM is being used for normal data transactions. The
auto refresh cycle can be performed once in 15.6us or a
burst of 2048 auto refresh cycles once in 32ms.
Self Refresh
The self refresh is another refresh mode available in the
SGRAM. The self refresh is the preferred refresh mode for
data retention and low power operation of SGRAM. In self
refresh mode, the SGRAM disables the internal clock and
all the input buffers except CKE. The refresh addressing
and timing is internally generated to reduce power
consumption.
The self refresh mode is entered from all banks idle state
by asserting low on CS , RAS , CAS and CKE with high
on WE . Once the self refresh mode is entered, only CKE
state being low matters, all the other inputs including clock
are ignored to remain in the self refresh.
The self refresh is exited by restarting the external clock
and then asserting high on CKE. This must be followed by
NOP’s for a minimum time of “tRC” before the SGRAM
reaches idle state to begin normal operation. If the system
uses burst auto refresh during normal operation, it is
recommended to used burst 2048 auto refresh cycles
immediately after exiting self refresh.
Define Special Function (DSF)
The DSF controls the graphic applications of SGRAM. If
DSF is tied to low, SGRAM function is 256K X 32 X 2 Bank
SDRAM. SDRAM can be used as an unified memory by the
appropriate DSF command. All the graphic function mode
can be entered only by setting DSF high when issuing
commands which otherwise would be normal SDRAM
commands.
SDRAM functions such as RAS Active, Write, and WCBR
change to SGRAM functions such as RAS Active with
WPB, Block Write and SWCBR respectively. See the
sessions below for the graphic functions that DSF controls.
Special Mode Register Set (SMRS)
There are two kinds of special mode registers in SGRAM.
One is color register and the other is mask register. Those
usage will be explained at “WRITE PER BIT” and ”BLOCK
WRITE” session. When A5 and DSF goes high in the same
cycle as CS , RAS , CAS and WE going low, load mask
register (LMR) process is executed and the mask registers
are filled with the masks for associated DQ’s through DQ
pins. And when A6 and DSF goes high in the same cycle
as CS , RAS , CAS and WE going low, load color
register (LCR) process is executed and the color register is
filled with color data for associated DQ’s through the DQ
pins. If both A5 and A6 are high at SMRS, data of mask
and color cycle is required to complete the write in the
mask register and the color register at LMR and LCR
respectively. The next clock of LMR or LCR, a new
commands can be issued. SMRS, compared with MRS, can
be issued at the active state under the condition that DQ’s
are idle. As in write operation, SMRS accepts the data
needed through DQ pins. Therefore it should be attended
not to induce bus contention. The more detailed materials
can obtained by referring corresponding timing diagram.
PRELIMINARY (October, 2001, Version 0.1)
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AMIC Technology, Inc.