A67L93181 Datasheet, PDF (16/18 Pages) AMIC Technology – 512K X 18, 256K X 36 LVTTL, Flow-through ZeBL SRAM

NOP, STALL and Deselect Cycles
1
2
3
4
CLK
CEN
CE
ADV/
LD
R/W
BWx
ADDRESS
A1
A2
A3
I/O
D(A1)
Q(A2)
COMMAND _WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
A67L93181/A67L83361
5
6
7
8
9
10
A4
Q(A3)
WRITE
D(A4)
STALL
D(A4)
NOP
A5
tKHQZ
Q(A5)
tKHQX
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
: Don't Care
: Undefined
Note : 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CEN being used to create a “pause.” A WRITE is
not performed during this cycle.
2. For this waveform, ZZ and OE are tied LOW.
3. CE represents three signals. When CE = 0, it represents CE = 0, CE2 = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The
most recent data may be from the input data register.
PRELIMINARY (July, 2005, Version 0.0)
16
AMIC Technology, Corp.