A25LQ080 Datasheet, PDF (14/58 Pages) AMIC Technology – 8Mbit, 3V Suspend/Resume, Dual/Quad-I/O Serial Flash Memory

A25LQ080 Series
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 3.) sets the
Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every
Page Program (PP), Dual Input Fast Program (DIFP), Quad
Input Fast Program (QIFP), Program OTP (POTP), Sector
Erase (SE), Block Erase (BE), and Chip Erase (CE) and Write
Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving
Chip Select ( S ) Low, sending the instruction code, and then
driving Chip Select ( S ) High.
Figure 3. Write Enable (WREN) Instruction Sequence
S
01 23 45 67
C
Instruction (06h)
DI
High Impedance
DO
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 4.) resets the
Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving Chip
Select ( ^S ) Low, sending the instruction code, and then driving
Chip The Write Enable Latch (WEL) bit is reset under the
following conditions:
ï¹£ Power-up
ï¹£ Write Disable (WRDI) instruction completion
ï¹£ Write Status Register (WRSR) instruction completion
ï¹£ Page Program (PP) instruction completion
ï¹£ Dual Input Fast Program (DIFP) instruction completion
ï¹£ Quad Input Fast Program (QIFP) instruction completion
ï¹£ Program OTP (POTP) instruction completion
ï¹£ Sector Erase (SE) instruction completion
ï¹£ Block Erase (BE) instruction completion
ï¹£ Chip Erase (CE) instruction completion
Figure 4. Write Disable (WRDI) Instruction Sequence
S
01 23 45 67
C
Instruction (04h)
DI
High Impedance
DO
(April, 2016, Version 1.0)
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