A616316 Datasheet, PDF (12/15 Pages) AMIC Technology – 64K X 16 BIT HIGH SPEED CMOS SRAM

AC Test Conditions
Input Pulse Levels
Input Rise And Fall Time
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
3 ns
1.5 V
See Figures 1 and 2
A616316 Series
OUTPUT
ZO=50Ω
RL=50Ω
VT=1.5V
Figure 1. Output Load
Data Retention Characteristics (TA = 0°C to 70°C)
Symbol
Parameter
Min.
VDR
VCC for Data Retention
3
ICCDR Data Retention Current
-
Chip Disable to Data Retention
tCDR
Time
tR
Operation Recovery Time
tRC = Read Cycle Time
0
TRC*
5V
480Ω
I/O
255Ω
5pF*
* Including scope and jig.
Figure 2. Output Load for tCLZ, tOLZ,
tCHZ, tOHZ, tWHZ, and tOW
Max.
5.5
1
-
-
Unit
V
mA
Conditions
CE ≥ VCC - 0.2V
VCC = 3.0V
CE ≥ VCC - 0.2V
VIN ≥ VCC - 0.2V or
VIN ≤ 0.2V
ns
See Retention Waveform
ms
PRELIMINARY (July, 2000, Version 0.0)
11
AMIC Technology, Inc.