LP621024D-I Datasheet, PDF (11/17 Pages) AMIC Technology – 128K X 8 BIT CMOS SRAM

AC Test Conditions
Input Pulse Levels
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
LP621024D-I Series
0V to 3.0V
5 ns
1.5V
See Figures 1 and 2
+5V
1800Ω
I/O
990Ω
30pF*
+5V
1800Ω
I/O
990Ω
5pF*
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Data Retention Characteristics (TA = -40°C to 85°C)
Figure 2. Output Load for tCLZ1,
tCLZ2, tOHZ, tOLZ, tCHZ1,
tCHZ2, tWHZ, and tOW
Symbol
VDR1
Parameter
VDR2 VCC for Data Retention
ICCDR1
Data Retention Current
ICCDR2
LL-Version
LL-Version
tCDR
Chip Disable to Data Retention Time
tR
Operation Recovery Time
Min.
2.0
2.0
-
-
0
5
Max.
5.5
5.5
20**
20**
-
-
Unit
Conditions
V
CE1 ≥ VCC - 0.2V
V
CE2 ≤ 0.2V
CE1 ≥ VCC - 0.2V or
CE1 ≤ 0.2V
VCC = 2.0V,
CE1 ≥ VCC - 0.2V
µA
CE2 ≥ VCC - 0.2V
VIN ≥ 0V
VCC = 2.0V
µA
CE2 ≤ 0.2V
VIN ≥ 0V
ns See Retention Waveform
ms
** LP621024D-55LLI/70LLI
ICCDR: Max. 2µA at TA = 0°C to + 40 °C
PRELIMINARY (August, 2002, Version 0.0)
11
AMIC Technology, Inc.