A63L83361_15 Datasheet, PDF (10/16 Pages) AMIC Technology – 256K X 36 Bit Synchronous High Speed SRAM

A63L83361
AC Characteristics (0°C ≤ TA ≤ 70°C, -25°C ≤ TA ≤ 85°C, VCC = 3.3V+5% or 3.3V-5%)
Symbol
Parameter
-6.5
-7.5
-8.5
Unit
Min. Max. Min. Max. Min. Max.
TKC Clock Cycle Time
7.5
-
8.5
-
10
-
ns
TKH Clock High Time
2.5
-
2.8
- 3.0 -
ns
TKL Clock Low Time
2.5
-
2.8
- 3.0 -
ns
TKQ Clock to Output Valid
-
6.5
-
7.5 - 8.5 ns
tKQX Clock to Output Invalid
3.0
-
3.0
- 3.0 -
ns
tKQLZ Clock to Output in Low-Z
2.5
-
2.5
- 2.5 -
ns
tKQHZ Clock to Output in High-Z
-
3.5
-
3.5 - 5.0 ns
tOEQ
OE to Output Valid
-
3.5
-
3.5 - 5.0 ns
tOELZ _{OE to Output in Low-Z}
0
-
0
-
0
-
ns
tOEHZ _{OE to Output in High-Z}
-
3.5
-
3.5 - 5.0 ns
Setup Times
TAS Address
1.5
-
2.0
- 2.0 -
ns
tADSS _{Address Status (} ADSC _, ADSP ₎
1.5
-
2.0
-
2.0
-
ns
tADVS _{Address Advance ( ADV )}
1.5
-
2.0
-
2.0
-
ns
tWS Write Signals
1.5
-
2.0
-
2.0
-
ns
( BW1, BW2 , BW3 , BW4 , BWE , GW )
TDS Data-in
1.5
-
1.5
- 2.0 -
ns
tCES _{Chip Enable ( CE , CE2, CE2 )}
1.5
-
2.0
-
2.0
-
ns
Hold Times
TAH Address
0.5
0.5
0.5
ns
tADSH _{Address Status ( ADSC , ADSP )}
0.5
0.5
0.5
ns
tAAH _{Address Advance ( ADV )}
0.5
0.5
0.5
ns
tWH Write Signal
0.5
0.5
0.5
ns
( BW1, BW2 , BW3 , BW4 , BWE , GW )
TDH Data-in
0.5
0.5
0.5
ns
tCEH _{Chip Enable (} CE _{, CE2,} CE2 ₎
0.5
0.5
0.5
ns
Note
5, 6
5, 6
8
5, 6
5, 6
7, 9
7, 9
7, 9
7, 9
7, 9
7, 9
7, 9
7, 9
7, 9
7, 9
7, 9
7, 9
(April, 2007, Version 1.0)
9
AMIC Technology, Corp.