LP62S2048-T Datasheet, PDF (1/17 Pages) AMIC Technology – 256K X 8 BIT LOW VOLTAGE CMOS SRAM

LP62S2048-T Series
256K X 8 BIT LOW VOLTAGE CMOS SRAM
Features
n Power supply range: 2.7V to 3.3V
n Access times: 70/100 ns (max.)
n Current:
Low power version:
Operating: 30mA (max.)
Standby: 50µA (max.)
Very low power version: Operating: 30mA (max.)
Standby: 10µA (max.)
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Output enable and two chip enable inputs for easy
application
n Data retention voltage: 2V (min.)
n Available in 32-pin SOP, TSOP, TSSOP (8 X 13.4mm)
and 36-pin CSP packages
General Description
The LP62S2048-T is a low operating current 2,097,152-
bit static random access memory organized as 262,144
words by 8 bits and operates on a low power supply
range: 2.7V to 3.3V. It is built using AMIC's high
performance CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2V.
Pin Configurations
n SOP
n TSOP/(TSSOP)
n CSP (Chip Size Package)
36-pin Top View
A17
1
A16
2
A14
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
I/O1
13
I/O2
14
I/O3
15
GND
16
32 VCC
31 A15
30 CE2
29
WE
28 A13
27 A8
26 A9
25 A11
24
OE
23
A10
22 CE1
21
I/O8
20
I/O7
19
I/O6
18
I/O5
17
I/O4
16
1
17
32
1
2
3
4
5
6
A ^A0
A1 CE2 A3
A6
A8
B I/O5 A2 WE A4 A7 I/O1
C I/O6
NC A5
I/O2
D GND
VCC
E VCC
GND
F I/O7
NC A17
I/O3
G I/O8 OE CE1 A16 A15 I/O4
H A9 A10 A11 A12 A13 A14
Pin No.
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Pin
Name
A11 A9 A8 A13 WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4
Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Pin
Name
A3 A2 A1 A0 I/O1 I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 I/O8 CE1 A10 OE
(August, 2001, Version 1.0)
1
AMIC Technology, Inc.