LP62S16256F-T Datasheet, PDF (1/14 Pages) AMIC Technology – 256K X 16 BIT LOW VOLTAGE CMOS SRAM

LP62S16256F-T Series
Preliminary
256K X 16 BIT LOW VOLTAGE CMOS SRAM
Features
n Operating voltage: 2.7V to 3.3V
n Access times: 70 ns (max.)
n Current:
Very low power version: Operating: 40mA (max.)
Standby: 10µA (max.)
n Full static operation, no clock or refreshing required
General Description
The LP62S16256F-T is a low operating current
4,194,304-bit static random access memory organized as
262,144 words by 16 bits and operates on low power
voltage from 2.7V to 3.3V. It is built using AMIC's high
performance CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Pin Configurations
n TSOP
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Data retention voltage: 2.0V (min.)
n Available in 44-pin TSOP and 48-ball CSP (6×8mm)
packages
The chip enable input is provided for POWER-DOWN,
device enable. Two byte enable inputs and an output
enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2.0V.
n CSP (Chip Size Package)
48-pin Top View
A4
1
A3
2
A2
3
A1
4
A0
5
CE
6
I/O1
7
I/O2
8
I/O3
9
I/O4
10
VCC
11
GND
12
I/O5
13
I/O6
14
I/O7
15
I/O8
16
WE
17
A17
18
A16
19
A15
20
A14
21
A13
22
44
A5
43
A6
42
A7
41
OE
40
HB
39
LB
38
I/O16
37
I/O15
36
I/O14
35
I/O13
34
GND
33
VCC
32
I/O12
31
I/O11
30
I/O10
29
I/O9
28
NC
27
A8
26
A9
25
A10
24
A11
23
A12
1
2
3
4
5
6
A LB OE A0 A1 A2 NC
B I/O9 HB A3 A4 CE I/O1
C I/O10 I/O11 A5
A6 I/O2 I/O3
D GND I/O12 A17 A7 I/O4 VCC
E VCC I/O13 NC A16 I/O5 GND
F I/O15 I/O14 A14 A15 I/O6 I/O7
G I/O16 NC A12 A13 _WE I/O8
H NC A8 A9 A10 A11 NC
PRELIMINARY (August, 2001, Version 0.2)
1
AMIC Technology, Inc.