LP62S1024A-I Datasheet, PDF (1/15 Pages) AMIC Technology – 128K X 8 BIT LOW VOLTAGE CMOS SRAM

LP62S1024A-I Series
Preliminary
128K X 8 BIT LOW VOLTAGE CMOS SRAM
Features
n Power supply range: 2.7V to 3.6V
n Access times: 55/70 ns (max.)
n Current:
Very low power version: Operating:(70NS)30mA(max.)
(55NS)40mA(max.)
Standby: 5uA (max.)
n Full static operation, no clock or refreshing required
General Description
The LP62S1024A-I is a low operating current 1,048,576-
bit static random access memory organized as 131,072
words by 8 bits and operates on a low power voltage:
2.7V to 3.6V. It is built using AMIC's high performance
CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Output enable and two chip enable inputs for easy
application
n Data retention voltage: 2V (min.)
n Available in 32-pin TSOP, TSSOP (8X13.4mm)
packages
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2V.
n TSOP/TSSOP
16
1
17
32
Pin No.
Pin
Name
Pin No.
Pin
Name
1
2
A11 A9
17 18
A3 A2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
19 20 21 22 23 24 25 26 27 28 29 30 31 32
A1 A0 I/O1 I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 I/O8 CE1 A10 OE
PRELIMINARY (August, 2001, Version 0.1)
1
AMIC Technology, Inc.