LP621024D-T Datasheet, PDF (1/16 Pages) AMIC Technology – 128K X 8 BIT CMOS SRAM

LP621024D-T Series
128K X 8 BIT CMOS SRAM
Features
n Single +5V power supply
n Access times: 55/70 ns (max.)
n Current:
Very low power version: Operating: 70mA (max.)
Standby: 50µA (max.)
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
General Description
The LP621024D-T is a low operating current 1,048,576-
bit static random access memory organized as 131,072
words by 8 bits and operates on a single 5V power
supply.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
n Common I/O using three-state output
n Output enable and two chip enable inputs for easy
application
n Data retention voltage: 2V (min.)
n Available in 32-pin DIP, SOP TSOP and TSSOP
(8 X 13.4mm) packages
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2V.
Pin Configurations
n DIP
NC
1
A16
2
A14
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
I/O1
13
I/O2
14
I/O3
15
GND
16
32
VCC
31 A15
30
CE2
29
WE
28
A13
27
A8
26 A9
25
A11
24
OE
23
A10
22 CE1
21
I/O8
20
I/O7
19
I/O6
18
I/O5
17
I/O4
n SOP
NC
1
A16
2
A14
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
I/O1
13
I/O2
14
I/O3
15
GND
16
n TSOP/(TSSOP)
32 VCC
31 A15
30
CE2
29
WE
28 A13
27 A8
26 A9
25 A11
24 OE
23
A10
22 CE1
21
I/O8
20
I/O7
19
I/O6
18
I/O5
17
I/O4
16
1
17
32
Pin No.
Pin
Name
Pin No.
Pin
Name
1
2
A11 A9
17 18
A3 A2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
19 20 21 22 23 24 25 26 27 28 29 30 31 32
A1
A0 I/O1 I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 I/O8 CE1 A10 OE
(August, 2001, Version 1.0)
1
AMIC Technology, Inc.