LP61L256B Datasheet, PDF (1/11 Pages) AMIC Technology – 32K X 8 Bit High SPEED LOW VCC CMOS SRAM

LP61L256B Series
32K X 8 Bit High SPEED LOW VCC CMOS SRAM
Features
n Single +3.3 volt power supply
n Access times: 12 ns (max.)
n Current: Operating: 100mA (max.)
Standby: 10mA (max.)
n Full static operation, no clock or refreshing required
General Description
The LP61L256B is a high-speed, low-power 262,144-bit
static random access memory organized as 32,768 words
by 8 bits that operates on a single 3.3V power supply.
Input and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
n All inputs and outputs directly TTL compatible
n Common I/O using three-state output
n Data retention voltage: 2V (min.)
n Available in 28-pin SOJ and TSOP packages
Minimum standby power is drawn by this device when CE
is at a high level, independent of the other input levels.
Data retention is guaranteed at a power supply voltage as
low as 2V.
Pin Configurations
n SOJ
A14
1
A12
2
A7
3
A6
4
A5
5
A4
6
A3
7
A2
8
A1
9
A0
10
I/O1
11
I/O2
12
I/O3
13
GND
14
28 VCC
27 WE
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19
I/O8
18
I/O7
17
I/O6
16
I/O5
15
I/O4
n TSOP
14
1
15
28
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Pin
Name
OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3
Pin No. 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Pin
Name
A2 A1 A0 I/O 1 I/O 2 I/O 3 GND I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 CE A10
(August, 2001, Version 1.0)
1
AMIC Technology, Inc.