LP61L1008A Datasheet, PDF (1/11 Pages) AMIC Technology – 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM

LP61L1008A
Preliminary
128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
Features
n Single 3.3V ± 10% power supply
n Access times: 8/10/12 ns (max.)
n Current: Operating: 160/155/150mA (max.)
Standby: 5mA (max.)
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL compatible
General Description
The LP61L1008A is a high speed 1,048,576-bit static
random access memory organized as 131,072 words by
8 bits and operates on a single 3.3V power supply.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Pin Configuration
n Center Power/Ground Pin Configuration
n Common I/O using three-state output
n Output enable and one chip enable inputs for easy
application
n Data retention voltage: 2.0V (min.)
n Available in 32-pin SOJ 300 mil package
The chip enable input is provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2.0V.
A0
1
A1
2
A2
3
A3
4
CE
5
I/O1
6
I/O2
7
VCC
8
GND
9
I/O3
10
I/O4
11
WE
12
A4
13
A5
14
A6
15
A7
16
32 A16
31
A15
30
A14
29
A13
28
OE
27
I/O8
26
I/O7
25
GND
24
VCC
23
I/O6
22
I/O5
21
A12
20 A11
19 A10
18 A9
17 A8
PRELIMINARY (August, 2001, Version 1.0)
1
AMIC Technology, Inc.