AMIS-49200 Datasheet, PDF (6/22 Pages) AMI SEMICONDUCTOR – Fieldbus MAU Chip

AMIS-49200 Fieldbus MAU
Data Sheet
RxA
RxS
TxE
TxS
POL
VSS
VSS
VSS
VSS
VSS
VCC
33 32 31 30 29 28 27 26 25 24 23
34
22
35
21
36
20
37
19
38
AMIS-49200
18
Fieldbus MAU
39
44 pin LQFP
17
40
16
41
15
42
14
43
13
44
12
1 2 3 4 5 6 7 8 9 10 11
VSS
VDRV
VSS
CRT
VCC
VDD
VO
SRTR
SRAO
SRSET
SRSETIN
Pin Information
Figure 3: AMIS 49200 Fieldbus MAU Pin Out
Table 1: Pin Numbers and Signal Description
Signal Name Pin No. I/O (Note 1)
VSS
1
Ground
VREF
2
AO
VMID
3
AO
N_PFAIL1
4
AI/O
N_PFAIL2
5
SHSETIN
6
SHSET
7
AI/O
AI
AO
SHUNT
VSS/
SGND
VSS
VSS
8
AI
9
Ground
10
Ground
11
Ground
SRSETIN
12
AI
SRSET
13
AO
SRAO
14
AO
SRTR
15
AI
VO
16
AO
Description
Connect to ground
Internal bandgap voltage (1.18V)
2V bias voltage for AC signals
Power fail alarm at VCC input. This pin is an open-drain output of negative
logic.
Power fail alarm at VDD input. This pin is an open-drain output of negative
logic.
Feedback (non-inverting) input for the shunt regulator
Divided voltage of VCC input. Feeding this voltage to SHSETIN pin results in
5V voltage at VCC.
Control pin of the shunt regulator. Its sink current (25mA max) is controlled
so that the voltage at SHSETIN is equal to V_REF (1.18V).
The current absorbed by SHUNT pin (25mA max) is fed to this pin, which
must be connected to the ground level
Ground
Ground
Feedback (inverting) input for the series regulator. The series regulator
controls its output (SRAO) to make this input voltage is equal to VREF
(1.18V).
Divided voltage of VO output. Feeding this voltage into SRSETIN pin results
in 3V at VO pin.
Output pin of an operational amplifier for the series regulator
Gate of a PMOS transistor for the series regulator
Output pin of the series regulator. (20mA max)
AMI Semiconductor – Jan. 07, M-20532-003
6
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