AMIS-50050 Datasheet, PDF (5/10 Pages) AMI SEMICONDUCTOR – Spread Spectrum Baseband Controller

AMIS-50050: Spread Spectrum Baseband Controller
Wireless Products
Data Sheet
Table 3: Pin Descriptions
Pin Name
Type
AGND1
Analog GND
GND1
Ground
VDD1
Vdd
OSC1
Input
OSC2
PLL[3:0]
TXD0
TXD1
EPOCH1
PN1
GND2
EXT[3:0]
VDD2
EXT[7:4]
EXT[9:8]
INT
RESET
CS
RD
WR
GND3
DATA[7:0]
ADDR[6:0]
VDD3
GND4
DUMP
EPOCH2
PN2
Padosc
Output
Output
Output
Output
Output
Ground
Output
Vdd
Output
Output
Output
Input
Input
Input
Input
Ground
BIDirection
Input
Vdd
Ground
Output
Output
Output
RCVRY
BIDirection
TEST
RXD1
RXD0
VREFD
AGND2
VCO2
AVDD2
Input
Analog I/O
Analog In
Analog In
Analog GND
Analog Input
Analog VDD
DACOUT1
Analog Output
DACOUT0
RBIAS
VREF
AGND3
Analog Output
Analog Input
Analog Input
Analog GND
RSSI1
Analog Input
RSSI2
AVDD3
AVDD1
VCO1
Analog Input
Analog VDD
Analog VDD
Analog I/O
Functional Description
Crystal oscillator or external reference input, this input is divided by OSCDIV to generate the reference clock for
the transmit PLL
Xtal osc output
Off-chip PLL programming; Bit0, Enable1, Bit1; Sclk, Bit2, Enable0, Bit3, Sdata
Transmit data “I” output
Transmit data “Q” output, or QAM output clock
Transmit PN generator Epoch signal, (68 pin PLCC package only)
Transmit PN generator output, can be internally disabled (PMR Bit 4)
External control port (lower bits), user defined functions for radio control
External control port (upper bits), user defined functions for radio control
External control port (upper bits), user defined functions for radio control (68 pin PLCC package only)
Active high – initiates an interrupt to the microprocessor
Active low – sets all registers to standby states
Active low – selects the chip for reading and writing via the µP interface
Active low – initiates a read operation via the µP interface
Active low – initiates a write operation via the µP interface
µP interface data bus
µP interface address bus
Integrate and dump control logic output
Receive PN Generator Epoch signal (68 pin PLCC package only)
Receive PN generator output
Clock recovery input for narrow band mode, track-on (active high) output for spread spectrum mode – indicates
to external circuitry that the PN code is locked and tracking the received PN code
Pin for manufacturing test only – should be tied to ground for normal operation
Receive data input “Q” or QAM mode output clock to external shift register
Receive data input “I”
Reference voltage for integrate and dump comparators and switches
Receive VCO control voltage output
Receive DAC output during TRACK operation – Note: DACOUT0 and DACOUT1 are provided in the event that
separate gain control is necessary for SLIP and TRACK operation
Receive PLL DAC output during SLIP operation
Current reference for DACs and analog buffers – nominal resistor value of 20kΩ to AGND3
Reference voltage for ADC and DACs – value is mid-scale between VDD and GND
Analog input to the ADC – received signal strength indicator from the RF receiver, range is zero to VREF (full
scale on the internal ADC)
Analog input to the ADC – received signal strength indicator from the RF receiver, range is zero to VREF (full
scale on the internal ADC) This input is not usable in “SLIP” mode.
Transmit VCO voltage control output
AMI Semiconductor – Sept. 06
5
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