AME8510 Datasheet, PDF (9/13 Pages) Analog Microelectronics – Micropower uP Watch Dog Timer

AME, Inc.
AME8510 / 8520 / 8530
Micropower µP Watch Dog Timer
n Detailed Description
The AME8510/8520/8530 are designed to interface with
the reset input of a microprocessor and to prevent CPU
execution errors due to power up, power down, and other
power supply errors. The AME8510/8520 also monitor
the CPU health by checking for signal transitions from
the CPU at the WDI input.
Reset Output
Each output pin in the family can be configured to be
either push/pull or open drain. In addition each output
may be either active high or active low with the condition
that parts with two outputs must have opposite polari-
ties. Active high reset outputs are denoted as RESET.
Active low reset outputs are denoted as RESETB. The
selection guide on page 3 of this data sheet shows all
possible combinations of output driver configuration.
A reset will be asserted if any of three things happen:
1) V drops below the threshold (V )
DD
TH
2) The MRB pin is pulled low.
3) The WDI pin does not detect a transition
within the watch dog interval (T_WD).
The reset will remain asserted for the prescribed reset
interval after:
1) V rises above the threshold (V )
DD
TH
2) MRB goes high
3) The watch dog timer has timed out causing
the reset to assert.
Manual Reset Input
The AME8510 and AME8530 feature a manual reset
feature (MRB). A logic low on the MRB pin asserts a
reset. The reset remains asserted as long as the MRB
pin remains low. After the MRB pin transitions to a high
state the reset remains asserted for the prescribed reset
interval (T_D2). The MRB pin is internally pulled up to VDD
by a 100KΩ resistor. It is internally debounced to reject
switching transients.
The MRB pin is ESD protected by diodes connected
to V_DD and GND. So the MRB pin should never be driven
higher than V_DD or lower than GND.
Watchdog Input
The AME8510 and AME8520 are equipped with a watch-
dog input (WDI). If the microprocessor does not produce
a valid logic edge at the the watchdog input (WDI) within
the prescribed watchdog interval (T_WD) then a reset as-
serts. The reset remains asserted for the required reset
interval (T ) At the end of the reset interval the reset is
D2
deasserted and the watchdog interval timer starts again
from zero.
If the watchdog input is left unconnected or is con-
nected to a tri-stated buffer the watchdog function is dis-
abled. As soon as the WDI input is driven either low or
high the watchdog function resumes with the watchdog
timer set to zero.
V_Release
V_DD
RESET
RESETB
T_D1
T_D2
50%
T_D1
T_D2
50%
Reset Timing Diagram
V_TH
50%
50%
V_TH
VDD
RESETB
T_D2
T_WD
T_D2
WDI
Watchdog Timing Diagram
9