AME9001 Datasheet, PDF (2/27 Pages) Analog Microelectronics – CCFL BACKLIGHT CONTROLLER

AME, Inc.
AME9001
CCFL Backlight Controller
n Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2
Pin Name
VREF
CE
SSC
RDELTA
FAULTB
RT2
VSS
OVP
CS
CSCOMP
CSDET
NC
OUTC
OUTAPB
OUTA
VBATT
VDD1
VDD
CT1
FB
COMP
BRIGHT
SSV
PNP
Pin Description
Reference. Compensation point for the 3.4V internal voltage reference. Must
have bypass capacitor connected here to VSS.
Chip enable. When low (<0.4V) the chip is put into a low current (~0uA)
shutdown mode.
Blanking interval ramp. During the first cycle this pin sources 1_mA. During
subsequent cycles it sources 150_mA. This is primarily used to provide a
"blanking interval" at the beginning of every dimming cycle to temporarily disable
the fault protection circuitry. (See application notes.)
A resistor connected from this pin to VBATT modulates the switching frequency
as a function of battery voltage.
0.1 _mF cap to VSS.
A resistor from this pin to VSS sets the minimum frequency of the VCO. The
voltage at this pin is 1.5V
Negative supply. Connect to system ground.
Over voltage protection input. Indirectly senses the voltage at the secondary of
the transformer through a resistor (or capacitor) divider. It will immediately turn
the circuit off if the voltage at OVP is over 3V. It will also turn the chip off if the
voltage at OVP is less than 250mV for 4 successive clock cycles after the
voltage at SSC has risen above 3V (SSC>3V).
Negative input of the auxiliary error amplifier(EA2). In this application it is
normally shorted to CSCOMP
Output of the auxiliary error amplifier(EA2). In this application the auxiliary error
amp is in a unity gain configuration and the voltage at CSCOMP =1.25V as long
as SSC > 1.25V. Otherwise CSCOMP is clamped to the voltage at SSC.
Current sense detect. Connect this pin to the CCFL current sense resistor
divider. If this pin is below 250mV for 4 consecutive clock cycles after SSC > 3V
then the circuit will shutdown.
Must float.
Drives one of the external NFETs, opposite phase of OUTAPB.
Drives one of the external NFETs, opposite phase of OUTC.
Drives the high side PFET.
Battery input. This is the positive supply for the OUTA driver.
Must be tied to VDD.
Regulated 5V supply input.
Sets the dimming cycle frequency. Usually about 100Hz.
Negative input of the voltage control loop error amplifier.
Output of the voltage control loop error amplifier.
Brightness control input. A DC voltage on this controls the duty cycle of the
dimming cycle. This pin is compared to a 3V ramp at the CT1 pin.
Soft start ramp for the voltage control loop. (20uA source current.)
Drives the base of an external PNP transistor used for the 5V LDO.